Chip I/O Testing via Internal Loop Path
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Solution Overview
Problem
High-speed bus testing devices for electronic devices are expensive, increasing the cost of manufacturing due to the need for specialized equipment to ensure correct operation of high-speed input/output functions.
Innovation Solution
A method and system for testing chips with high-speed I/O functions using a low-cost, low-speed testing environment by enabling both transmission and receiving mechanisms within the chip, allowing for testing via an inner loop path within the high-speed bus interface circuit, which includes a transmission circuit, receiving circuit, adjusting circuit, data connecting circuit, and strobe signal connecting circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external high-speed testing device is introduced to test high-speed I/O functions, then the correctness of electronic device operations can be ensured, but the cost of the electronic device increases significantly
Solution Approach 1:
The chip performs self-testing by utilizing its own internal transmission and receiving mechanisms. The testing function is integrated within the chip itself, allowing it to test its own high-speed I/O capabilities without requiring external high-speed testing equipment, thereby reducing manufacturing costs while ensuring operational correctness
Solution Approach 2:
The transmission and receiving mechanisms are designed to serve dual purposes: they function as normal operational components during chip operation and as testing components when activated in test mode. This multi-functionality eliminates the need for separate dedicated testing hardware, reducing overall system cost
2Ease of manufacture
If a low-cost testing environment is used for high-speed chips, then manufacturing cost decreases, but the ability to accurately test high-speed I/O functions is compromised
Solution Approach 1:
A data connecting circuit serves as an intermediary that routes test data between the transmission and receiving mechanisms. This intermediary structure enables the creation of a closed-loop test path within the chip, allowing accurate high-speed signal transmission and reception testing using low-cost testing equipment
Solution Approach 2:
The patent creates a virtual model of the high-speed I/O transmission path by routing test signals through the chip's own transmission and receiving mechanisms. This internal copying of the actual operational path allows accurate testing of high-speed capabilities without requiring expensive external high-speed testing equipment
Data Source
AI summary
A chip operating method is provided which includes enabling a transmission mechanism or a receiving mechanism of the chip while normally operating the chip. The method further includes enabling both of the transmission mechanism and the receiving mechanism of the chip while testing the chip.