Semiconductor Chip Joint Layout for Single-Reflow Thin Packaging
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Solution Overview
Problem
Existing semiconductor devices face challenges in manufacturing thin designs due to the need for separate reflow processes for different joints, which can lead to connection failures and increased manufacturing time, and are prone to failure due to differences in joint volumes and temperatures.
Innovation Solution
A semiconductor device configuration with a package substrate, a first semiconductor chip, an adhesive layer, a second semiconductor chip, first joints, and second joints, where the adhesive layer fixes the substrate to the first chip, and the second chip is positioned opposite with overlapping and non-overlapping regions, using joints with distinct fusion points to facilitate a single reflow process and reduce failure risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate reflow processes are used for different joints, then connection reliability is improved, but manufacturing time is increased and device thickness is increased
Solution Approach 1:
The patent applies parameter changes by using joints with different fusion points (first joint material with fusion point of 200-250°C, second joint material with fusion point of 150-200°C). This allows a single reflow process to selectively fuse different joints at different temperatures, achieving reliable connections for both chip-to-substrate and chip-to-chip interfaces without requiring separate reflow processes, thereby reducing manufacturing time while maintaining connection reliability
2Reliability
If separate reflow processes are used for different joints, then connection reliability is improved, but device thickness is increased
Solution Approach 1:
The patent uses joints with different fusion points to enable a single reflow process that simultaneously handles both first joints (chip-to-substrate) and second joints (chip-to-chip). This eliminates the need for multiple reflow processes and associated spacing requirements, allowing for thinner device design while maintaining reliable connections through controlled solidification order
3Adaptability or versatility
If joints with different volumes are used, then device functionality is improved, but failure risk is increased due to temperature differences
Solution Approach 1:
The patent addresses the failure risk from temperature differences by using joint materials with different fusion points. The first joint material (fusion point 200-250°C) and second joint material (fusion point 150-200°C) are specifically selected so that during a single reflow process, one joint solidifies before the other. This controlled solidification order prevents connection failures that would otherwise occur due to simultaneous solidification of joints with different volumes and thermal characteristics
Solution Approach 2:
The patent applies beforehand cushioning by pre-designing the fusion point difference between joint materials to anticipate and prevent connection failures. By selecting materials with appropriately different fusion points, the patent creates a buffer that allows the larger-volume joint to solidify first, cushioning against the thermal stress and volume contraction that would otherwise cause failures in the smaller-volume joint during cooling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for the production of thinner devices by minimizing the distance between chips and substrates, shortening manufacturing time, and reducing the likelihood of joint failures by controlling the solidification order of joints based on their fusion points.
Implementation Method 1
A fusion point of the first joint is lower than a fusion point of the second joint
Data Source
AI summary
A semiconductor device includes a substrate, a first semiconductor chip, an adhesive layer, a second semiconductor chip, a first joint, and a second joint. The adhesive layer fixes the substrate to the first semiconductor chip. The second semiconductor chip includes a first region overlapping the first semiconductor chip in a thickness direction of the substrate and a second region excluding the first region. The first joint is disposed between the first semiconductor chip and the first region of the second semiconductor chip and electrically connects the first semiconductor chip to the second semiconductor chip. The second joint is disposed between the substrate and the second region of the second semiconductor chip, is larger than the first joint in volume, and electrically connects the substrate to the second semiconductor chip. A fusion point of the first joint is lower than a fusion point of the second joint.