Chip-Kill Decoding for Multiple NAND Wordline Failures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing systems fail to recover data from NAND flash memory devices when multiple wordlines fail due to physical defects, as they cannot obtain necessary channel information for error correction, leading to unrecoverable data.
Innovation Solution
Implementing a chip-kill scheme that uses iterative decoding with scheduling and soft information updates based on XOR parity bits to recover failed wordlines, where the decoding order is determined by the number of error bits, and soft information is updated using convergence and divergence criteria.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing chip-kill schemes are used for multiple wordline failures, then simple XOR over all data in a superblock is performed, but data recovery fails when two or more wordlines fail due to physical defects where no channel information can be obtained
Solution Approach 1:
The patent segments the decoding process into multiple iterations with different decoding orders. In the first iteration, all codewords are decoded in parallel. In subsequent iterations, failed codewords are identified and decoded sequentially in a specific order based on error bit counts, while successful codewords are skipped. This segmentation allows the system to handle multiple wordline failures by breaking down the complex recovery task into manageable stages.
Solution Approach 2:
The patent performs preliminary decoding of all codewords in the first iteration to identify which ones have failed. Based on the results of this preliminary action, the system determines the decoding order for subsequent iterations, prioritizing codewords with fewer error bits. This preliminary assessment enables the system to plan the recovery strategy before executing the complex sequential decoding process.
2Reliability
If iterative decoding with scheduling is implemented to recover multiple failed wordlines, then data recovery success rate improves, but decoding time and computational resources increase
Solution Approach 1:
The patent implements a dynamic decoding schedule that adapts based on the results of each iteration. The decoding order is not fixed but is determined dynamically by counting error bits in each codeword and arranging them in ascending order. This dynamic approach allows the system to optimize the decoding sequence for each specific failure scenario, improving recovery success while managing decoding time efficiently by processing easier-to-recover codewords first.
Solution Approach 2:
The system uses feedback from each decoding iteration to adjust the decoding strategy for the next iteration. After the first iteration, the system identifies which codewords failed and uses this feedback to determine the decoding order in subsequent iterations. The feedback mechanism also tracks the number of error bits to prioritize codewords that are more likely to succeed, thereby optimizing the use of decoding time and resources.
3Reliability
If soft information is updated using XOR parity bits and convergence criteria, then error correction capability improves for multiple failed wordlines, but computational complexity increases
Solution Approach 1:
The patent uses XOR parity bits as an intermediary to update soft information for failed codewords. Instead of directly attempting to correct errors in multiple failed wordlines simultaneously, the system uses the parity information from successfully decoded codewords as a mediator to guide the recovery process. This intermediary approach simplifies the computational complexity by breaking down the error correction task into smaller, more manageable steps that leverage the parity information iteratively.
Data Source
AI summary
Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when reading data from a superblock of the memory, where the decoding of multiple wordlines failed, a computer system schedules the decoding of failed wordlines based on quantity of bit errors and updates soft information based on convergence or divergence of the scheduled decoding. Such a computer system significantly reduces decoding failures associated with data reads from the memory and allows improved data retention in the memory.