Chip Lamination via Backside Holding to Prevent Circuit Damage
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Solution Overview
Problem
The existing chip-on-chip (CoC) semiconductor device manufacturing method risks damaging the circuit-forming layer of the second semiconductor chip during lamination due to the bonding tool's suction and holding mechanism, which can disconnect the circuit and reduce the reliability of the semiconductor device.
Innovation Solution
The semiconductor device is designed with a chip laminate structure where the first semiconductor chip's circuit-forming layer faces the second semiconductor chip's circuit-forming layer, allowing the non-formed surface of the second semiconductor chip to be held during lamination, minimizing the risk of damage to the circuit-forming layer, and incorporating a reduced number of through-electrodes with wider spacing in the IF chip to increase rigidity and reduce stress-induced cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the bonding tool suctions and holds the one surface of the second semiconductor chip on which the circuit-forming layer has been formed, then the chip can be held for lamination, but the circuit-forming layer may be damaged and reliability reduced
Solution Approach 1:
The patent inverts the conventional lamination approach by holding the second semiconductor chip through its non-circuit-forming layer surface (back surface) rather than the circuit-forming layer surface. This reversal allows the bonding tool to grip the chip without contacting or damaging the delicate circuit-forming layer, while still achieving secure holding for the lamination process.
2Reliability
If through-electrodes are densely spaced to connect electrodes, then electrical connection is achieved, but stress may cause cracking and reduce reliability
Solution Approach 1:
The patent changes the spatial parameter of through-electrode spacing by intentionally increasing the distance between adjacent through-electrodes. This parameter modification reduces the stress concentration on individual through-electrodes and the surrounding circuit-forming layer, thereby preventing stress-induced cracking while maintaining adequate electrical connection functionality.
Data Source
AI summary
A chip laminate in this semiconductor device has a structure consisting of a first semiconductor chip and a second semiconductor chip laminated together. The first semiconductor chip has a circuit-forming layer and a first bump electrode formed on one surface and a second bump electrode formed on the other surface. The second semiconductor chip has a circuit-forming layer and a third bump electrode formed on one surface and a fourth bump electrode formed on the other surface. The first semiconductor chip and the second semiconductor chip are laminated together such that the circuit-forming layer on the first semiconductor chip and the circuit-forming layer on the second semiconductor chip face each other and the first and third bump electrodes are electrically connected to each other.