Semiconductor Chip-Layer Layout for Compact High-Speed CML I/O
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Solution Overview
Problem
Existing semiconductor devices face challenges in high-speed data transmission due to the difficulty in integrating CML circuits with different transistor types on the same substrate, leading to increased circuit area and manufacturing costs.
Innovation Solution
A semiconductor device design incorporating a semiconductor chip with a first circuit and a second circuit connected via a layer containing a metal oxide channel formation region, allowing for high-speed data transmission and reduced circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CML circuit and different circuit are formed using different transistors on different substrates, then high-speed data transmission is achieved, but the area of the printed circuit board increases and manufacturing cost increases
Solution Approach 1:
The patent merges the CML circuit and different circuit onto a single substrate by forming both circuit types using the same transistor structure (first transistor for CML, second transistor for different circuit). This integration eliminates the need for separate substrates and reduces the overall circuit board area while maintaining high-speed data transmission capability.
Solution Approach 2:
The patent creates a universal transistor design that can serve multiple functions - the same transistor structure is used to form both CML circuits and other types of circuits. This multi-functional approach allows different circuit types to coexist on one substrate, reducing complexity and area requirements.
2Speed
If CML circuit and different circuit are formed using different transistors on different substrates, then high-speed data transmission is achieved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple circuit types on a single substrate using a unified transistor fabrication process. This merging approach reduces manufacturing complexity by eliminating the need to handle, align, and assemble multiple separate substrates, thereby reducing manufacturing costs while preserving high-speed performance.
Solution Approach 2:
The patent changes the fabrication parameters to allow the same transistor structure to serve different circuit functions. By standardizing the transistor formation process and adjusting only the circuit configuration parameters, the manufacturing process becomes simpler and more cost-effective while maintaining the ability to achieve high-speed data transmission.
3Ease of manufacture
If CML circuit and different circuit can be formed over the same substrate using the same transistors, then manufacturing cost is reduced, but the circuit area increases
Solution Approach 1:
The patent applies local quality by optimizing the spatial arrangement and density of transistors within the circuit. By carefully positioning the first and second transistors and their interconnections in a compact configuration, the circuit achieves high integration density, reducing the overall circuit area while maintaining manufacturability on a single substrate.
Solution Approach 2:
The patent utilizes three-dimensional integration techniques and vertical interconnections to reduce the planar footprint of the circuit. By stacking components and using via connections through multiple layers, the circuit achieves compact area occupation while remaining manufacturable using standard single-substrate processes.
Data Source
AI summary
A semiconductor device being capable of high-speed data transmission and having a reduced circuit area is provided. The semiconductor device includes a semiconductor chip, an external terminal, and a layer including two facing surfaces. The semiconductor chip is provided on one surface side of the layer, and the external terminal is provided on the other surface side of the layer at least in a region not overlapping with the semiconductor chip. The semiconductor chip includes a first circuit including a first transistor, and the layer includes a second circuit including a second transistor. The first circuit is electrically connected to the second circuit, and the second circuit is electrically connected to the external terminal. The second transistor includes a metal oxide in a channel formation region. Note that the second circuit may be a CML circuit. In addition, an insulator may be provided above the one surface of the layer and on a side surface of the semiconductor chip.