Quasi-Monolithic Chip Layers With Integrated Capacitors for Power Delivery
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Solution Overview
Problem
Current IC packaging technologies face challenges with low vertical and horizontal interconnect density, which affects power delivery and transient support, particularly in high-performance compute systems, due to limitations in on-die and package-integrated capacitors.
Innovation Solution
The quasi-monolithic hierarchically integrated packaging architecture integrates capacitors within multiple layers of IC dies in a dielectric material with high-density interconnects, including planar, deep trench, and via capacitors, to enhance power delivery and transient support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional on-die and package-integrated capacitors are used, then device complexity is reduced, but interconnect density and power delivery capability deteriorate
Solution Approach 1:
The patent transitions from planar (2D) capacitor layouts to three-dimensional (3D) vertical capacitor structures integrated within the die stack. By utilizing the vertical dimension between die layers, the design achieves high interconnect density without expanding the horizontal footprint, effectively resolving the contradiction between quantity of interconnect and device complexity.
Solution Approach 2:
Capacitors are nested within the hierarchical die stack structure, with vertical capacitors positioned between adjacent die layers. This nesting approach allows capacitors to occupy the vertical space already defined by the stacked architecture, increasing interconnect density while maintaining the existing package structure without adding external complexity.
2Power
If vertical interconnect density is increased, then power delivery capability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The vertical interconnect structures and capacitor positions are predetermined during the die stacking design phase. Alignment marks and registration features are pre-defined on each die layer, allowing subsequent assembly processes to achieve precise vertical alignment without requiring ultra-precision manufacturing. The preliminary structuring of interconnect locations simplifies the manufacturing precision requirement.
Solution Approach 2:
The vertical interconnect path is segmented into discrete sections corresponding to each die layer interface. By breaking down the continuous vertical interconnect into manageable segments at each stacking interface, the manufacturing precision requirement is distributed across multiple simpler alignment operations rather than requiring one complex high-precision operation.
3Reliability
If capacitors are integrated within die layers, then transient support is improved, but device complexity increases
Solution Approach 1:
The vertical interconnect structures serve multiple functions: they provide electrical connection between die layers, act as capacitor electrodes, and establish power delivery paths. This multi-functionality allows capacitors to be integrated without adding separate dedicated structures, thereby improving transient support while minimizing the increase in device complexity.
Solution Approach 2:
The capacitor structure is merged with the vertical interconnect structure. The same conductive elements that provide inter-layer electrical connection also serve as capacitor plates, eliminating the need for separate capacitor components and reducing integration complexity while enhancing transient support capability.
Data Source
AI summary
Embodiments of a microelectronic assembly comprise: a plurality of layers of IC dies in a dielectric material, adjacent layers in the plurality of layers being coupled together by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; a package substrate coupled to a first side of the plurality of layers by second interconnects; a support structure coupled to a second side of the plurality of layers by third interconnects, the second side being opposite to the first side; and capacitors in at least the plurality of layers or the support structure. The capacitors are selected from at least planar capacitors, deep trench capacitors and via capacitors.