Semiconductor Chip Layout With In-Chip Align Keys and TEG Patterns
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Solution Overview
Problem
Current semiconductor manufacturing processes face inefficiencies due to the need for optimizing layouts of elements on substrates to reduce unnecessary areas and improve chip formation, leading to increased complexity and resource utilization.
Innovation Solution
Incorporating align key patterns and test element group (TEG) patterns within chip regions and scribe lanes on a substrate, allowing for more efficient use of space and integration of testing capabilities within a single exposure area, thereby reducing the area required for scribe lanes and increasing chip density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If align key patterns and TEG patterns are placed only in scribe lanes, then manufacturing testing and alignment are enabled, but scribe lane area increases reducing chip density
Solution Approach 1:
The patent merges the functions of align key patterns and TEG patterns from the scribe lanes into the chip regions. Specifically, align key patterns are integrated into the chip regions where they serve dual purposes: enabling alignment during photolithography exposure processes and providing test functionality. This consolidation eliminates the need for separate scribe lane areas dedicated to these patterns, thereby reducing scribe lane width and increasing chip density while maintaining manufacturing testing capability.
2Productivity
If more chip regions are formed per shot group, then chip density increases, but layout complexity increases making optimization difficult
Solution Approach 1:
The patent applies segmentation by dividing the chip region into distinct functional zones: a first region containing align key patterns and TEG patterns, and a main region containing unit devices. This segmentation allows each zone to be optimized independently for its specific function while maintaining overall layout simplicity. The modular approach facilitates easier layout optimization as the number of chip regions per shot group increases, as each chip region follows a standardized segmented structure.
3Productivity
If scribe lane area is reduced to increase chip density, then manufacturing efficiency improves, but space for alignment and testing patterns is reduced
Solution Approach 1:
The patent transitions the placement of align key patterns and TEG patterns from the one-dimensional scribe lane structure to the two-dimensional chip region space. By utilizing the chip region area for these patterns instead of relying on peripheral scribe lanes, the layout effectively uses available space in a different dimensional arrangement. This allows scribe lanes to be minimized or eliminated while ensuring adequate space for alignment and testing patterns within the chip regions themselves.
Data Source
AI summary
A semiconductor device may include a plurality of chip regions on a substrate, at least one scribe lane surrounding each of the plurality of chip regions on the substrate, a plurality of first align key patterns and a plurality of first test element group patterns included in the plurality of chip regions, and a plurality of second align key patterns and a plurality of second test element group patterns included in the at least one scribe lane.