Automated Chip Layout Using Pre-Trained Models

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Solution Overview

Problem

The manual layout of chips is time-consuming, inefficient, and prone to errors, leading to poor accuracy and increased costs due to the complex process of arranging multiple devices on a chip, where mistakes can result in material waste and inefficiencies.

Innovation Solution

A method that involves determining a logic diagram and device list for the chip, using a pre-trained layout model to calculate the arrangement positions of devices, improving efficiency and accuracy by automating the layout process and reducing human error.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If manual layout method is used, then flexibility and adaptability are maintained, but layout time increases and productivity decreases

Engineering Contradiction:

Improvelayout speedVSAvoidmanual operation level

Core Design Contradiction:

ProductivityVSExtent of automation

Solution Approach 1:

The patent replaces the manual mechanical layout process with an automated computer-based system that uses trained models to generate chip layouts automatically, substituting human manual operations with automated computational processes to improve productivity

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent performs preliminary training of layout models using historical layout data before actual chip layout generation, preparing the system in advance with learned patterns and rules to enable fast automated layout generation without manual intervention during production

Inventive Principle:

Principle #10Preliminary action

2Reliability

If manual layout method is used, then complex logic can be handled, but error rate increases and reliability decreases

Engineering Contradiction:

Improvelayout accuracyVSAvoidmanual operation level

Core Design Contradiction:

ReliabilityVSExtent of automation

Solution Approach 1:

The patent replaces manual layout operations with automated model-based generation, eliminating human errors such as typos and misplaced components while maintaining the ability to handle complex logic through trained computational models

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent uses historical layout data as feedback to continuously train and improve the layout models, allowing the system to learn from past successes and errors to enhance layout accuracy and reliability over time

Inventive Principle:

Principle #23Feedback

3Productivity

If manual layout method is used, then customization is possible, but time consumption increases and productivity decreases

Engineering Contradiction:

Improvelayout efficiencyVSAvoidlayout time

Core Design Contradiction:

ProductivityVSDuration of action of moving object

Solution Approach 1:

The patent performs preliminary training of layout models on historical data to capture design patterns and rules, enabling the automated system to generate customized layouts quickly without manual intervention during the actual layout process

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent creates a universal layout model that can handle multiple chip types and design requirements through single training process, allowing the same automated system to generate diverse customized layouts efficiently without requiring separate manual processes for each case

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12045552B2Layout method of a chip and electronic equipment

Publication Date: 2024.07.23 BEIJING BOE OPTOELECTRONCIS TECH CO LTD

AI summary

A layout method of a chip includes: determining a logic diagram corresponding to a chip to be laid out and a device list corresponding to the logic diagram; and determining a layout diagram of the chip to be laid out, according to the logic diagram, the device list, and a pre-trained layout mode. The layout diagram includes at least an arrangement position, in the chip to be laid out, of each device in the device list.