Chip Layout Reduces Parasitic Capacitance via Segmented Storage Arrays
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Solution Overview
Problem
The existing DRAM chip layout with top-level wiring introduces parasitic capacitance, leading to reduced transmission speed and increased power consumption, which becomes exacerbated as chip capacity increases, potentially closing the eye diagram and affecting signal transmission.
Innovation Solution
The chip layout is redesigned with a storage module comprising two storage array groups and a control module positioned between them, with shorter connection lines that reduce parasitic capacitance and improve signal transmission speed, by optimizing the ratio of storage arrays and the placement of pins and control circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If top-level wiring is introduced to improve transmission speed, then chip operating speed is improved, but parasitic capacitance increases
Solution Approach 1:
The chip is divided into a first storage array group and a second storage array group, with the control module positioned between them. This segmentation allows pins to be located on the side of the first storage array group away from the second, enabling shorter connection lines for pin-related circuits while maintaining overall chip functionality through the distributed storage array groups.
Solution Approach 2:
The control module is strategically positioned between the first and second storage array groups to optimize connection distances. The first connection line extends from pins to the control module with a specific length constraint, while the second connection line connects the control module to both storage array groups, creating localized optimization of signal paths.
2Speed
If pin-related circuits are placed in the middle section of the chip, then transmission speed is improved, but connection line length increases
Solution Approach 1:
The chip layout employs asymmetric placement of the control module between the first and second storage array groups. The first connection line has a controlled length that is less than the distance from the control module to the side of the second storage array group, creating an asymmetric configuration that optimizes signal transmission while managing connection line lengths.
3Quantity of substance
If chip capacity increases, then storage capacity is improved, but parasitic capacitance impact increases
Solution Approach 1:
The storage arrays are divided into multiple groups (first storage array group and second storage array group) with the control module positioned between them. This segmentation allows the chip to accommodate increased capacity while maintaining shorter connection lines for critical pin-related circuits, thereby controlling parasitic capacitance impact even as overall chip capacity increases.
Data Source
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AI summary
The present disclosure provides a chip and an electronic device. The chip includes a storage module, pins, a control module, a first connection line and a second connection line. The storage module includes a first storage array group and a second storage array group, which respectively include a plurality of first storage arrays and a plurality of second storage arrays. The pins are located on a side of the first storage array group away from the second storage array group. The control module is located between the first storage array group and the second storage array group. The first connection line connects the pins with the control module; and the second connection connects the control module with the first storage array group and the second storage array group. The first connection line has a length less than the distance from the control module to a side of the second storage array group away from the control module. The chip reduces the parasitic capacitance introduced by the first connection line.