Chip Layout Optimization via Minimum Wire Length Sequence Pairs
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Solution Overview
Problem
Existing VLSI chip design methods prioritize minimizing the chip area over reducing the total wire length between rectangular circuit modules, leading to inadequate power dissipation and delay reduction, and inefficient use of materials.
Innovation Solution
A chip layout method that initializes a maximum preset wire length and iteratively generates and refines sequence pairs to represent the positional relationship between modules, using a model to minimize the total wire length, converting the problem into a maximum-cost flow problem solvable within polynomial time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If existing algorithms prioritize optimization of total chip area, then the chip area is minimized, but the total wire length between rectangular circuit modules increases leading to higher power dissipation and delay
Solution Approach 1:
The patent changes the optimization parameter from chip area to total wire length. By transforming the objective function of the layout optimization problem, the algorithm now minimizes wire length while maintaining legitimate placement constraints, directly addressing the contradiction by prioritizing the previously neglected parameter.
Solution Approach 2:
The patent introduces a feedback mechanism where the wire length is calculated based on pin coordinates and continuously optimized through iterative algorithms. The system monitors wire length as a feedback parameter and adjusts module positions to reduce it, creating a closed-loop optimization process that resolves the contradiction between area and wire length.
2Ease of manufacture
If rectangular circuit modules are connected through their centers using existing methods, then the connection is simple to implement, but the total wire length is not minimized leading to suboptimal performance
Solution Approach 1:
The patent performs preliminary ordering of rectangular circuit modules before physical connection. By establishing an optimal sequence based on wire length minimization criteria before actual placement, the system prepares the best possible configuration in advance, avoiding the need for complex real-time adjustments while achieving minimal wire length.
Solution Approach 2:
The patent transforms the static center-to-center connection approach into a dynamic optimization process. The module positions and connection paths are no longer fixed but are continuously adjusted based on wire length calculations, allowing the system to adapt and minimize total wire length while maintaining implementation feasibility.
3Reliability
If more metal wires are used to connect circuit modules, then the chip performance can be maintained, but the material cost increases and utilization rate decreases
Solution Approach 1:
The patent changes the optimization focus from area to wire length, which directly correlates with material usage. By minimizing wire length as the primary objective, the system naturally reduces metal wire consumption while maintaining connection functionality, thereby improving material utilization rate without sacrificing chip performance.
Solution Approach 2:
The patent converts the previously harmful effect of excessive wire length (which wasted material and increased cost) into a beneficial optimization target. By making wire length minimization the explicit objective, the system transforms material waste from an unavoidable consequence into a controlled parameter that is actively reduced, turning a negative outcome into a positive design criterion.
Data Source
AI summary
A chip layout method based on a minimum total wire length, includes: initializing a total wire length to a preset value, initializing a number of iterations, randomly generating a sequence pair to represent a positional relationship between rectangular circuit modules, inputting the sequence pair to a model, and solving to obtain a sequence pair having a minimum wire length within the number of iterations; changing a field operator of the sequence pair to obtain a new one, inputting the new sequence pair to the model, retaining, if an obtained total wire length is less than the original total wire length, the new sequence pair, or otherwise, abandoning the new sequence pair; repeating the above operation till the number of iterations is reached; and outputting a minimum total wire length, and coordinates of each rectangular circuit module to obtain the chip layout based on the minimum total wire length.