Chip-On-Lead Package With Hidden Small Chip Between Leads
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Solution Overview
Problem
Conventional Chip-On-Lead (COL) semiconductor packages experience uneven encapsulant distribution and mold flow imbalance due to smaller chips extruding from leads, leading to warpage and reduced memory capacity when packaging multiple chips.
Innovation Solution
The smaller chip is hidden between leads, forming a die-holding cavity, allowing the larger chip to overlap and encapsulate it, ensuring balanced encapsulant distribution and enabling increased stacking of larger chips for enhanced memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If small chips are stacked on top of leads in conventional COL packages, then memory capacity can be increased, but uneven encapsulant distribution occurs leading to warpage
Solution Approach 1:
The patent places the first chip (smaller chip) inside the die-holding cavity formed by the leads, effectively nesting it within the lead structure. This allows the chip to be positioned below the level of the leads, preventing it from protruding and disrupting encapsulant flow. The second chip (larger chip) is then stacked on top of the leads, creating a nested configuration where the smaller chip is hidden within the lead cavity while the larger chip provides the primary memory capacity. This resolves the contradiction by enabling increased memory capacity through stacking while maintaining uniform encapsulant distribution.
Solution Approach 2:
The patent utilizes the vertical dimension by creating a die-holding cavity that extends downward from the lead level. The first chip is positioned in this cavity below the lead plane, while the second chip is positioned above the lead plane. This three-dimensional arrangement allows both chips to coexist without interfering with encapsulant flow, as the smaller chip is recessed into the structure rather than protruding from it. This dimensional reorganization resolves the warpage issue while maintaining high memory capacity.
2Ease of manufacture
If small chips are extruded from leads during molding, then packaging is simplified, but unbalanced mold flow occurs causing warpage
Solution Approach 1:
The patent preemptively addresses the mold flow imbalance problem by designing the die-holding cavity to recess the first chip below the lead level before molding occurs. This preliminary structural arrangement prevents the small chip from protruding and disrupting encapsulant flow during the molding process. The cavity acts as a pre-prepared space that guides the encapsulant flow evenly around the leads and chips, eliminating the warpage issue before it can occur. This maintains packaging simplicity while ensuring manufacturing precision.
3Quantity of substance
If multiple chips are stacked to increase memory capacity, then storage is improved, but encapsulant distribution becomes unbalanced
Solution Approach 1:
The patent implements a nested configuration where the first chip is positioned inside the die-holding cavity formed by the leads, and the second chip is stacked on top of the leads. This nested arrangement allows multiple chips to be packaged together for increased memory capacity while maintaining symmetric encapsulant distribution. The first chip recessed in the cavity and the second chip on top create a balanced structure that prevents warpage, thereby improving both memory capacity and package structural stability simultaneously.
Data Source
AI summary
A Chip-On-Lead (COL) type semiconductor package having small chip hidden between leads is revealed. The lower surfaces of the leadframe's leads are attached to a wiring substrate and the leads are horizontally bent to form a die-holding cavity. A smaller chip is disposed on the wiring substrate by passing through the die-holding cavity to be on the same disposing level with the leads. At least a larger chip is disposed on the leads to overlap the smaller chip so that the small chip does not extrude from the leads. The encapsulant encapsulates a plurality of internal parts of the leads, the wiring substrate, and the larger chip. Therefore, the conventional unbalance issue of mold flow above and below the leads leading to cause excessive warpage can be avoided and numbers of stacked larger chips can be increased to have larger memory capacities.