Chip-Level Flop Insertion for Buffer Overflow Prevention
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Solution Overview
Problem
In integrated circuit design, buffer overflow occurs due to mismatched data and flow control signal delays, leading to queue overflow, which is difficult to address without redesigning the physical layout of the chip.
Innovation Solution
Inserting flip-flops (flops) at the chip-level to introduce signal latency between sender and receiver blocks, ensuring the sum of data line and flow control line delays is less than the buffer depth, thereby preventing buffer overflow and meeting physical design timing requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the sender node transmits data rapidly to improve throughput, then productivity increases, but the receiver node's queue overflows due to limited buffer depth
Solution Approach 1:
Flip-flops are inserted as intermediary elements between the sender and receiver blocks to mediate the data transmission timing. These flip-flops act as buffer stages that temporarily hold data, allowing the sender to transmit at high rates while the receiver processes at slower rates without causing queue overflow.
Solution Approach 2:
The patent calculates the required number of flip-flops in advance based on buffer depth and transmission parameters, then inserts them preemptively into the data path. This preliminary action ensures that sufficient latency is built into the system before overflow issues occur, allowing high-speed transmission without risking buffer overflow.
2Reliability
If additional delay elements are inserted to increase signal latency and prevent overflow, then buffer overflow prevention improves, but the overall signal transmission delay increases
Solution Approach 1:
The patent precisely calculates the optimal number of flip-flops to insert based on parameters such as buffer depth, data transmission rate, and flow control signal latency. By changing the parameter of flip-flop count from a generic value to a precisely calculated value, the system achieves minimum necessary latency to prevent overflow while minimizing unnecessary delay to throughput.
3Reliability
If the physical layout of the chip is redesigned to adjust buffer size and timing, then buffer overflow prevention improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the timing adjustment function from the physical layout design stage and implements it separately using inserted flip-flops in the logical design. This separation allows timing and buffer management to be optimized without requiring complex physical layout redesigns, thereby reducing device complexity and manufacturing overhead.
Data Source
AI summary
Systems and methods for inserting flops at the chip-level to produce a signal delay for preventing buffer overflow are disclosed herein. Shells of modules described in an RTL description and their connections are analyzed to determine a signal latency between a sender block and a receiver block. The logical interfaces of the shells are grouped in a structured document with associated rules. Flops are inserted between the sender block and the receiver block to introduce a flop delay to meet physical design timing requirement and prevent a buffer of the receiver block from overflowing due to data that is already in-flight when a flow control signal is sent by the receiver block. The sum of a delay on a data line and a delay on a flow control line measured in clock cycles must be less than a depth of the buffer.