Chip-Level Switching for USB 3.1 and DP 1.3 Interface Integration
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Solution Overview
Problem
Conventional electronic devices with USB 3.1 and DP 1.3 interfaces require complex system board configurations and may introduce latency and signal integrity issues due to the need for discrete physical layers and multiplexers for simultaneous operation.
Innovation Solution
A semiconductor chip with a switch that can route signals from both USB 3.1 and DP 1.3 controllers via a single physical layer, allowing for chip-level switching between independent and simultaneous modes to optimize signal propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multiplexer is provided on the system board to enable simultaneous operation of USB 3.1 and DP 1.3 signals, then both interfaces can operate simultaneously, but the board complexity increases and latency or signal integrity issues are introduced
Solution Approach 1:
The patent merges the USB 3.1 and DP 1.3 controllers and their physical layers onto a single semiconductor chip, eliminating the need for separate board-level multiplexers. The chip integrates multiple interface controllers and physical layers in one package, reducing board complexity while maintaining simultaneous operation capability through internal switching mechanisms.
Solution Approach 2:
The semiconductor chip is designed as a universal platform that can simultaneously support both USB 3.1 and DP 1.3 interfaces through a single chip implementation. The chip's internal switch can route signals from either controller to the appropriate physical layer, enabling multi-functional operation without requiring separate dedicated paths for each interface.
2Reliability
If discrete physical layers are used for USB 3.1 and DP 1.3 controllers, then each interface has dedicated signal paths, but board complexity increases and signal integrity issues are introduced
Solution Approach 1:
The patent combines multiple physical layers (USB 3.1 PHY and DP 1.3 PHY) onto a single semiconductor chip, eliminating the need for separate discrete physical layers on the board. This integration reduces the number of signal paths and connection points, thereby reducing board complexity while maintaining signal integrity through controlled internal routing.
Solution Approach 2:
The patent introduces an internal switch as an intermediary component within the chip that mediates between the different controllers and physical layers. This switch can selectively route signals from USB 3.1 or DP 1.3 controllers to their respective physical layers, providing flexible signal routing while maintaining dedicated paths for each interface and thus preserving signal integrity.
3Adaptability or versatility
If a multiplexer is used to route signals between interfaces, then signal routing flexibility is achieved, but latency is introduced
Solution Approach 1:
The patent replaces the mechanical/board-level multiplexer with an electronic switch integrated within the semiconductor chip. This internal switch operates at a faster speed and introduces minimal latency compared to external board-level multiplexers. The switch can rapidly route signals between different controllers and physical layers based on real-time needs, providing flexibility while minimizing time loss.
Data Source
AI summary
Various semiconductor chips and computing devices are disclosed. In one aspect a semiconductor chip is provided that includes a first interface controller, a first physical layer connected to the first interface controller, a second interface controller, a second physical layer connected to the second interface controller, and a switch connected between the first interface controller and the second interface controller and the first physical layer and the second physical layer. The switch is operable in one mode to route signals to/from the first interface controller via the first physical layer and route signals to/from the second interface controller via the second physical layer and in another mode to route signals to/from both the first interface controller and the second interface controller via the first physical layer.