Vector Signaling for Chip-to-Chip Links With Reduced SSO Noise

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Solution Overview

Problem

Modern computer systems face challenges in achieving high-speed, low-latency data transfers between memory controllers and memory devices while minimizing Simultaneous Switched Output (SSO) noise and power consumption, especially in wide I/O operations, due to constraints on pin count and power utilization.

Innovation Solution

The implementation of vector signaling codes that use three or more distinct signal levels, such as ternary or quaternary signaling, to reduce or eliminate SSO noise, with optimized encoder and decoder designs that are power-efficient and compatible with both high-speed logic and DRAM processes, allowing for reduced power consumption and minimal noise immunity trade-offs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If single-ended signaling is used for wide I/O operations, then data transfer throughput is improved, but Simultaneous Switched Output (SSO) noise and power consumption increase

Engineering Contradiction:

Improvedata transfer throughputVSAvoidSSO noise

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the signaling parameter from binary (2 levels) to multi-level (3 or 4 levels) signaling. This allows encoding more bits per symbol while reducing the number of simultaneous transitions needed, thereby reducing SSO noise while maintaining high data transfer throughput.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent transitions from traditional time-division multiplexing to vector signaling that utilizes multiple signal levels (dimensions) simultaneously. By encoding data across multiple voltage levels rather than just time slots, the system achieves high throughput with fewer simultaneous switching events.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Speed

If single-ended signaling is used for wide I/O operations, then data transfer speed is improved, but power consumption increases

Engineering Contradiction:

Improvedata transfer speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent employs multi-level signaling parameters where each signal level carries more information bits. This reduces the total number of signal transitions required for a given data rate, thereby lowering dynamic power consumption while maintaining high data transfer speed.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The vector signaling scheme enables continuous data transmission with optimized transition patterns that minimize unnecessary switching events. By maintaining signal continuity and reducing idle transitions, the system achieves high speed with reduced power consumption.

Inventive Principle:

Principle #20Continuity of useful action

3Object-generated harmful factors

If more signal levels are used in vector signaling, then SSO noise is reduced, but encoding and decoding complexity increases

Engineering Contradiction:

ImproveSSO noiseVSAvoidencoder and decoder complexity

Core Design Contradiction:

Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent segments the encoding and decoding processes into modular functional blocks (e.g., parallel encoders, lookup tables, state machines). This segmentation allows complex multi-level vector signaling to be implemented through manageable, reusable components, reducing overall system complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent uses pre-computed lookup tables and standardized encoder/decoder templates that can be copied and instantiated multiple times. This approach avoids re-implementing complex algorithms for each signaling instance, thereby reducing design complexity while supporting multiple signal levels.

Inventive Principle:

Principle #26Copying

4Use of energy by moving object

If vector signaling codes with three or more signal levels are implemented, then power consumption is reduced, but manufacturing precision requirements increase

Engineering Contradiction:

Improvepower consumptionVSAvoidsignal level discrimination precision

Core Design Contradiction:

Use of energy by moving objectVSManufacturing precision

Solution Approach 1:

The patent incorporates margin design and noise tolerance buffering into the signal level definitions. By预留ing sufficient voltage margins between signal levels and designing robust decision thresholds, the system maintains power efficiency while accommodating manufacturing variations and signal noise.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The patent implements feedback mechanisms in the receiver that monitor signal quality and adjust decision thresholds dynamically. This feedback allows the system to compensate for manufacturing tolerances and process variations, maintaining reliable operation with reduced power consumption despite precision challenges.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS9357036B2Methods and systems for chip-to-chip communication with reduced simultaneous switching noise

Publication Date: 2016.05.31 KANDOU LABS SA

AI summary

Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.