Chip Misalignment Measurement in Fan-Out Panel Level Packages
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Solution Overview
Problem
As semiconductor chip integration density increases, the challenge of measuring misalignment in chip placement becomes more complex due to fixed bump distances and size constraints, affecting handling and testing, particularly in the fabrication of fan-out panel level packages.
Innovation Solution
A method involving scanning to obtain images of chips on a substrate, calculating absolute and relative offsets of reference and subordinate chips, and using these offsets to determine misalignment, which is then used to improve the reliability of the exposure process during package fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional misalignment measurement methods are used, then measurement accuracy can be maintained, but measurement speed is slow and affects productivity
Solution Approach 1:
The patent divides the misalignment measurement process into two distinct phases: a learning phase where offset information is collected from multiple chips to establish reference data, and a subsequent measurement phase where pre-stored offset data is used to rapidly calculate misalignment. This segmentation allows the system to maintain high accuracy through comprehensive offset learning while achieving fast measurement speeds during actual production by avoiding repeated complex image processing.
Solution Approach 2:
The patent performs offset learning and stores reference offset information in advance before actual misalignment measurements are needed. By pre-processing and storing the offset data during a learning phase, the system eliminates time-consuming image processing steps during production measurements, thereby significantly improving measurement speed without sacrificing accuracy.
2Quantity of substance
If chip size is decreased to increase integration density, then more chips can be placed on substrate, but misalignment measurement becomes more difficult and handling becomes problematic
Solution Approach 1:
The patent introduces offset information as an intermediary parameter that simplifies the measurement of tiny misalignments in small chips. Instead of directly measuring absolute positions of minute chip features, the system uses pre-learned offset data between corresponding features on different chips to calculate relative misalignment, making measurement feasible even for very small chip sizes.
Solution Approach 2:
The patent transforms the measurement approach by changing from absolute position measurement to relative offset measurement. By using pre-stored offset information and calculating relative positions rather than absolute coordinates, the system can accurately measure misalignment in miniaturized chips where direct measurement would be too difficult.
3Reliability
If fixed bump distances are maintained according to JEDEC standards, then compatibility is ensured, but the ability to increase integration density is limited
Solution Approach 1:
The patent replaces traditional mechanical/physical constraints (fixed bump pitch according to JEDEC standards) with a software-based measurement and compensation system. By using image processing and offset calculation algorithms, the system can accommodate varying bump configurations and densities while maintaining measurement accuracy, effectively substituting rigid physical standard compliance with flexible computational methods.
Data Source
AI summary
A method of measuring misalignment of chips, a method of fabricating a fan-out panel level package using the same, and a fan-out panel level package fabricated thereby are provided. The measuring method may include obtaining images by scanning chips on a substrate, obtaining absolute offsets of reference chips with respect to the substrate in the images, obtaining relative offsets of subordinate chips with respect to the reference chips in the images, and calculating misalignments of the chips based on the absolute offsets and the relative offsets.