Chip Architecture for ML Algorithm Execution
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Solution Overview
Problem
Implementing machine learning algorithms against large databases is timely and manually intensive due to the inefficiencies in current computer architectures, which struggle to efficiently execute operations against vast data sets.
Innovation Solution
A method and system that generate a chip architecture based on a dataflow graph, determining the chronological order of operations and creating an architecture with an access engine and execution engine to efficiently retrieve and execute algorithms against databases, optimizing the execution of machine learning algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional computer architectures are used to execute machine learning algorithms against large databases, then the system can process data, but the execution is timely and manually intensive
Solution Approach 1:
The system segments the machine learning algorithm execution into distinct phases: data retrieval phase handled by an access engine and computation phase handled by an execution engine. This segmentation allows parallel processing and optimizes each phase independently, reducing overall processing time while maintaining high productivity.
Solution Approach 2:
The patent introduces a dataflow graph as an intermediary structure that mediates between the machine learning algorithm and the database. The dataflow graph translates algorithm operations into optimized data retrieval and computation sequences, enabling efficient execution without manual intervention and reducing processing time.
2Extent of automation
If conventional computer architectures are used, then the system can execute algorithms, but the implementation is manually intensive
Solution Approach 1:
The system implements self-service through automatic generation of the dataflow graph from the machine learning algorithm and automatic scheduling of operations. The access engine and execution engine automatically execute operations without manual intervention, significantly increasing automation level while making the system easier to operate.
Solution Approach 2:
The system performs preliminary actions by pre-compiling the machine learning algorithm into a dataflow graph structure before execution. This preliminary processing automatically optimizes the execution plan and operation sequencing, enabling fully automated execution without manual effort while maintaining ease of operation through simple algorithm input.
3Productivity
If a dedicated chip architecture is generated based on dataflow graph, then execution efficiency improves, but system complexity increases
Solution Approach 1:
The chip architecture is designed with multi-functionality, where the access engine and execution engine can handle various machine learning algorithms and data types through a unified dataflow graph framework. This universality allows the same architectural structure to efficiently execute different algorithms without requiring separate dedicated hardware for each algorithm type, thus improving productivity while controlling complexity.
Solution Approach 2:
The chip architecture incorporates dynamic scheduling capabilities where the dataflow graph can adaptively sequence operations based on data characteristics and algorithm requirements. This dynamic approach allows the system to optimize execution efficiency for different workloads while using a single flexible architectural platform rather than multiple static dedicated architectures, managing complexity through programmability rather than hardware diversity.
Data Source
AI summary
A method for database management that includes receiving an algorithm from a user. Based on the algorithm, a hierarchical dataflow graph (hDFG) may be generated. The method may further include generating an architecture for a chip based on the hDFG. The architecture for a chip may retrieve a data table from a database. The data table may be associated with the architecture for a chip. Finally, the algorithm may be executed against the data table, such that an action included in the algorithm is performed.


