Chip Module Port Allocation for Read-Write Bandwidth
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Solution Overview
Problem
Current CPU-memory bus systems face limitations in increasing read/write bandwidth due to crosstalk and inefficient I/O port allocation, particularly with fixed unidirectional SerDes transmission and equal sending and receiving bandwidths not matching random memory read/write directions.
Innovation Solution
A chip module with a control module that dynamically switches selection ports between read and write ports based on transmit/receive requirements, adjusting the ratio of read and write ports to match operational needs, thereby optimizing port allocation and increasing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a fixed unidirectional SerDes transmission manner is used, then the signal transmission rate is improved, but the adaptability to random memory read/write directions deteriorates
Solution Approach 1:
The patent applies dynamics by making the SerDes transmission direction configurable and switchable. The system dynamically adjusts the transmission direction (read or write) based on the actual memory access patterns and workload requirements, rather than being fixed in one direction. This allows the system to adapt to random memory read/write directions while maintaining high signal transmission rates through SerDes technology.
Solution Approach 2:
The patent changes the parameter of transmission direction from fixed to variable. By allowing the SerDes interface to switch between read-dominated and write-dominated modes based on system requirements, the patent resolves the contradiction between maintaining high transmission rates and adapting to random access patterns.
2Device complexity
If equal sending and receiving bandwidths are allocated, then the I/O port allocation is simplified, but the matching with random memory read/write directions deteriorates
Solution Approach 1:
The patent implements dynamic bandwidth allocation where the sending and receiving bandwidth ratios can be adjusted based on actual memory access patterns. The system monitors read/write operations and dynamically reconfigures the bandwidth distribution, allowing it to match random memory access directions without requiring complex static allocation schemes.
Solution Approach 2:
The patent changes the bandwidth allocation parameter from fixed equal distribution to variable distribution. By allowing the bandwidth ratio to be adjusted based on system needs, the patent achieves better matching with random memory read/write directions while managing complexity through controlled parameter variation.
3Speed
If parallel bus transmission is used, then the read/write speed between CPU and memory is improved, but the crosstalk between signals increases
Solution Approach 1:
The patent replaces the traditional parallel mechanical bus system with a SerDes (serializer/deserializer) based system. Instead of multiple parallel signal lines that are prone to crosstalk, the system uses serial transmission with differential signaling, which significantly reduces electromagnetic interference and crosstalk while maintaining or improving transmission speed.
4Quantity of substance
If a large wiring area is allocated for parallel bus, then the connection capacity is improved, but the printed circuit board area is increased
Solution Approach 1:
The patent substitutes the wide parallel bus wiring with a more compact SerDes implementation. The serial transmission requires significantly less wiring space on the printed circuit board while providing equivalent or superior connection capacity through higher data rates and more efficient use of the physical medium.
Data Source
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AI summary
This application provides a chip module, a communication system, and a port allocation method. The chip module has a plurality of first ports, at least some or all of the first ports are first selection ports, and each first selection port may act as a write port or a read port. The chip module further includes a first control module. The first control module controls, based on a transmit/receive requirement of the chip module, the first selection port to be switched to a read port or a write port, to match the transmit/receive requirement of the chip module. In the foregoing technical solution, the first selection port may selectively act as a read port or a write port, so that switching can be performed based on an operating state of the chip module, thereby increasing a read/write bandwidth of the chip module. In addition, the first control module controls an operating state of the first selection port, to flexibly adjust a quantity of read ports and a quantity of write ports of the chip module.