Chip Moisture Barrier Layout Around I/O Openings and Edge Corners
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Solution Overview
Problem
Photonics integrated circuit (PIC) chips are prone to moisture ingress due to input/output openings, which can lead to damage of the moisture barrier during fabrication processes like chip dicing and handling, resulting in a heightened risk of moisture ingress.
Innovation Solution
A dielectric moisture barrier structure comprising a first portion along the input/output opening, a second portion along the edge of the chip, and a third portion coupling the first and second portions, with the third portion positioned away from the corner to prevent damage, and additional crack stops to absorb fabrication-related stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thin dielectric moisture barrier layer is used around the chip periphery and input/output openings, then the moisture barrier provides effective protection against moisture ingress, but the moisture barrier is subject to damage at the outer corners during chip dicing, handling, or other fabrication processes
Solution Approach 1:
The moisture barrier is divided into multiple segments: a first moisture barrier portion extending along a side of the I/O opening, a second moisture barrier portion extending along the edge of the chip, and a third moisture barrier portion coupling the first and second portions. This segmentation allows each portion to be optimized for its specific function and location, reducing stress concentration at corners while maintaining overall barrier integrity.
Solution Approach 2:
The moisture barrier transitions from a simple linear path to a multi-dimensional structure with portions extending in different directions and coupling at strategic locations. The third moisture barrier portion creates a dimensional extension that provides structural reinforcement and stress distribution, preventing corner damage while maintaining the barrier's protective function.
2Stress or pressure
If crack stops are chamfered at certain corners of the IC chip to reduce stress, then stress concentration is reduced, but the chamfers do not address the damage to the moisture barrier at the input/output openings
Solution Approach 1:
Different portions of the moisture barrier are designed with different configurations tailored to their specific locations and functions. The first portion along the I/O opening is optimized for protecting the opening, the second portion along the edge provides peripheral protection, and the third coupling portion is specifically designed to bridge these areas while distributing stress. This localized optimization ensures each section addresses the specific challenges of its position.
Solution Approach 2:
The multi-portion moisture barrier structure is designed and implemented before chip dicing and handling processes occur. The strategic positioning and coupling of the three moisture barrier portions preemptively addresses potential stress concentration and damage risks, rather than attempting to repair damage after it occurs during fabrication processes.
Data Source
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AI summary
A structure includes an integrated circuit chip in a substrate, and an I/O opening extending inwardly from an edge of the integrated circuit chip. A dielectric moisture barrier includes a first portion extending along a side of the I/O opening, a second portion extending along the edge of the integrated circuit chip, and a third portion coupling the first moisture barrier portion to the second moisture barrier portion to complete the moisture barrier between the edge of the integrated circuit chip and the I/O opening. The third portion is distanced from the corner of the integrated circuit chip where the I/O opening meets the edge of the chip to prevent damage to the moisture barrier from fabrication processes, such as chip dicing, chip handling or other processes. Various crack stop configurations are also provided to further protect the moisture barrier from damage.