Semiconductor Chip Mounting Structure With Inorganic Moisture Barrier
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Solution Overview
Problem
Semiconductor devices face challenges in achieving a better moisture-proof effect and gas barrier property, as existing solutions are not sufficient to protect against humidity and gas permeation.
Innovation Solution
A semiconductor device design featuring a first inorganic insulating layer with metal posts and a semiconductor chip mounting part, where a second inorganic insulating layer covers the entire semiconductor chip mounting part, providing a continuous moisture-resistant and gas-barrier layer, formed using techniques like CVD and ALD, with specific layer structures and materials to enhance adhesion and airtightness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polymer deposition film of a para-xylylene compound is used to provide moisture-proof effect, then moisture resistance is improved, but gas barrier property is insufficient
Solution Approach 1:
The patent employs a composite inorganic insulating layer structure combining a first inorganic insulating layer (e.g., SiO2, SiN) and a second inorganic insulating layer (e.g., Al2O3, TiO2) with different material compositions. This composite structure provides both moisture resistance and gas barrier properties that single-material polymer films cannot achieve, as the inorganic materials offer superior impermeability to both moisture and gases while maintaining electrical insulation.
Solution Approach 2:
The patent transitions from a single-layer polymer film to a multi-layer inorganic insulating structure with vertical stacking of different material layers. This dimensional approach (adding layer depth and material diversity) enables simultaneous achievement of moisture proofing and gas barrier functions that cannot be obtained with conventional single-layer organic coatings.
2Reliability
If conventional moisture-proof methods are used, then moisture resistance is improved, but adhesion and airtightness are insufficient
Solution Approach 1:
The patent utilizes CVD and ALD deposition techniques to precisely control the thickness, density, and compositional parameters of each inorganic insulating layer. By optimizing deposition parameters such as layer thickness (e.g., 50-200 nm per layer), deposition temperature, and material stoichiometry, the patent achieves enhanced adhesion between layers and improved airtightness that conventional polymer deposition cannot provide.
Solution Approach 2:
The first inorganic insulating layer acts as an intermediary between the substrate and the second inorganic insulating layer, providing graded adhesion and stress distribution. This intermediate layer prevents direct contact between potentially incompatible materials, reducing delamination risk and improving overall structural integrity and airtightness.
3Productivity
If semiconductor devices are miniaturized, then device density is improved, but moisture-proof protection becomes more difficult to maintain
Solution Approach 1:
The patent divides the moisture-proof protection function into multiple segmented inorganic insulating layers with distinct material compositions and functions. This segmentation allows each layer to be optimized for specific protection needs (e.g., first layer for adhesion and basic moisture barrier, second layer for enhanced gas barrier and airtightness), enabling effective protection even as device dimensions are reduced and area for coating is minimized.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly improves moisture resistance and gas barrier properties, meeting Category 2 requirements for electronic devices by reducing moisture vapor transmission rates, while ensuring the reliability and miniaturization of metal posts.
Implementation Method 1
a second inorganic insulating layer covers the entirety of the second surface and the entirety of the side surface of the semiconductor chip mounting part
Implementation Method 2
formed using techniques like CVD and ALD
Implementation Method 3
formed using techniques like CVD and ALD
Data Source
AI summary
A semiconductor device includes a first inorganic insulating layer, a metal post embedded in the first inorganic insulating layer, a semiconductor chip mounting part stacked on the first inorganic insulating layer, and a second inorganic insulating layer. The metal post has first and second end faces that are exposed in the first and second opposite surfaces, respectively, of the first inorganic insulating layer. The semiconductor chip mounting part has first and second opposite surfaces and a side surface connecting the first and second opposite surfaces of the semiconductor chip mounting part. The first surface of the semiconductor chip mounting part contacts the second surface of the first inorganic insulating layer. The second inorganic insulating layer covers the entirety of the second surface and the entirety of the side surface of the semiconductor chip mounting part. The second inorganic insulating layer is continuous with the first inorganic insulating layer.