Dynamic Chip Network Topology Configuration via Host-Side Connection Sensing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional chip networks suffer from inflexible topologies, leading to insufficient bandwidth and high latency, and are unable to efficiently support dynamic changes in network topology, which are necessary for meeting the computing demands of artificial intelligence applications.
Innovation Solution
A method where a central processing unit enumerates and manages multiple chips, instructs them to perform connection sensing operations, aggregates connection information, and dynamically configures logical connections based on service requirements to construct a flexible topology, increasing bandwidth and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional fixed topology chip networks are used, then device complexity is reduced, but bandwidth is insufficient and latency is high
Solution Approach 1:
The patent implements dynamic topology configuration where the host can programmatically configure logical connection relationships among chips based on different service requirements. The system transitions from fixed physical topology to flexible logical topology that can be dynamically adjusted through software control, enabling bandwidth optimization without proportionally increasing hardware complexity.
Solution Approach 2:
The patent creates a universal topology management mechanism that can support multiple network topologies (ring, mesh, tree, etc.) and different service scenarios through a single configurable system. The host manages chip connections universally through standardized interfaces and protocols, reducing the need for dedicated hardware for each topology type while maintaining high bandwidth performance.
2Adaptability or versatility
If dynamic topology changes are supported, then adaptability is improved, but connection sensing and management complexity increases
Solution Approach 1:
The patent implements automatic connection sensing mechanisms where chips autonomously detect and report their connection status to the host. The system performs self-diagnosis and self-configuration through automated protocols, reducing the manual intervention and complexity required for topology management while enhancing adaptability to dynamic changes.
Solution Approach 2:
The patent establishes feedback loops where connection status information is continuously monitored and reported back to the host. Based on this feedback, the system dynamically adjusts logical topology configurations to maintain optimal performance. The feedback mechanism enables automatic adaptation without requiring complex manual sensing procedures.
3Measurement precision
If connection sensing operations are performed frequently, then topology accuracy is improved, but communication latency increases
Solution Approach 1:
The patent implements periodic connection sensing operations where the host queries chip connection status at predetermined intervals rather than continuously. This periodic approach maintains adequate topology accuracy for AI workloads while significantly reducing the time overhead compared to continuous sensing, achieving an optimal balance between precision and latency.
Solution Approach 2:
The patent performs connection sensing and topology configuration in advance before AI computing tasks begin. By pre-establishing the logical topology and connection relationships, the system avoids real-time sensing delays during actual computation, thereby maintaining high measurement accuracy without increasing operational latency.
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
Embodiments of the present disclosure relate to a method an apparatus, an electronic device and a computer readable storage medium for determining connection relationships among a plurality of chips. The method includes determining identity information of a plurality of chips managed by a host, the plurality of chips being connected by respective inter-chip communication interfaces for inter-chip communication. The method further includes allowing one or more of the plurality of chips to acquire identity information of other chips connected to the inter-chip communication interface of the one or more chips. The method further includes reading identity information of the other chips by means of a management interface of the one or more chips with regard to communicating with the host, so as to determine connection relationships among the plurality of chips. The technical solution according to the present disclosure determines, according to an inter-chip communication interface of each chip, a chip connected thereto, so as to create and maintain a physical connection matrix of the chip network on a host side, thereby facilitating the detection of a connection fault of the chip network and dynamic configuration of a topology of the chip network.