Chip Node Grouping by Interconnect Topology and Compute Power

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Solution Overview

Problem

In deep learning training scenarios, performance of chips is reduced due to long distances and small interconnection bandwidths between computing nodes with the same computing power, affecting training efficiency when data synchronization is performed.

Innovation Solution

A chip management apparatus with a device management unit that obtains interface information to determine physical interconnection relationships between computing nodes, allowing for grouping into collaboration groups based on computing power and physical interconnection, ensuring tasks are allocated to nodes with same power and high-speed bus connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If parallel tasks are allocated to computing nodes with the same computing power but located far apart with small interconnection bandwidth, then computing power utilization is improved, but data synchronization performance deteriorates

Engineering Contradiction:
Improvecomputing power utilizationVSAvoiddata synchronization speed
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The system differentiates between different physical locations and interconnection qualities of computing nodes. Computing nodes are grouped into collaboration groups based on their physical interconnection relationships, ensuring that nodes with high-speed bus connectivity are assigned together while nodes with slower connections are separated. This local quality differentiation resolves the contradiction by optimizing data synchronization speed within each group while maintaining overall computing power utilization across the distributed system.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system segments computing nodes into multiple collaboration groups based on their physical interconnection relationships and computing power characteristics. Each collaboration group is independently managed for task allocation, allowing parallel tasks to be assigned within groups where high-speed data synchronization is guaranteed. This segmentation enables the system to maintain high computing power utilization while ensuring fast data synchronization within each segmented group.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If computing nodes with different computing powers process parallel tasks, then task allocation flexibility is improved, but processing efficiency deteriorates

Engineering Contradiction:
Improvetask allocation flexibilityVSAvoidprocessing efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The system changes the parameter of computing node grouping from arbitrary or location-based to computing power-based collaboration groups. By grouping nodes with identical computing power together, the system ensures that parallel tasks allocated within a collaboration group can be processed at the same speed, eliminating waiting time and improving processing efficiency. At the same time, the system maintains adaptability by allowing dynamic task allocation across multiple collaboration groups based on task requirements and node availability.

Inventive Principle:
Principle #35Parameter changes

3Speed

If computing nodes are physically interconnected with high-speed bus, then data synchronization speed is improved, but system complexity increases

Engineering Contradiction:
Improvedata synchronization speedVSAvoidsystem complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The system employs a device management unit that automatically discovers and identifies the interconnection relationships between computing nodes. Rather than requiring manual configuration or complex external management infrastructure, the device management unit self-services by obtaining interface information from computing nodes and autonomously determining their physical interconnection status. This self-service approach enables fast data synchronization through high-speed bus connections while minimizing system complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12554668B2Chip management apparatus and related method
Publication Date: 2026.02.17 HUAWEI TECH CO LTD
  • US12554668B2 patent drawing
  • US12554668B2 patent drawing
  • US12554668B2 patent drawing

AI summary

A chip management apparatus includes a device management unit, a system management unit, and N computing nodes. The device management unit is configured to: obtain interface information of each of the N computing nodes, and determine an interconnection relationship between the N computing nodes based on the interface information of the N computing nodes. The system management unit is configured to group, based on the interconnection relationship between the N computing nodes and computing power information of the N computing nodes, the N computing nodes into M first collaboration groups. Each of the M first collaboration groups includes at least one computing node, and the at least one computing node included in each first collaboration group has a same computing power and is physically interconnected.