Chip-on-chip semiconductor device with recessed bump connections

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Solution Overview

Problem

Existing semiconductor packages face challenges in achieving reduced weight and thickness while maintaining high electrical performance, particularly in small-sized electronic devices, due to limitations in vertical stacking of semiconductor chips without gold wires, which can lead to signal transmission delays and increased power consumption.

Innovation Solution

A chip-on-chip (COC) semiconductor device fabrication method involving a first semiconductor device with metal wiring having discontinuous spots and a second semiconductor device with bumps, where the bumps are aligned and connected to the discontinuous spots, enhancing electrical connection reliability and reducing mechanical and electrical damages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Weight of stationary object

If semiconductor chips are stacked vertically without gold wires, then weight and thickness are reduced, but electrical connection reliability deteriorates due to potential damages when connecting upper and lower chips

Engineering Contradiction:

Improveweight of semiconductor packageVSAvoidelectrical connection reliability

Core Design Contradiction:

Weight of stationary objectVSReliability

Solution Approach 1:

The patent divides the connection interface into two segments: a recess region formed in the upper semiconductor chip and a bump structure on the lower semiconductor chip. This segmentation allows the bump to fit into the recess, creating a mechanically robust connection that prevents damage during stacking while maintaining wire-free connectivity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The recess region is formed in advance in the upper semiconductor chip before stacking. This pre-formed recess acts as a cushioning structure that protects the bump from mechanical damage during the connection process, thereby improving electrical connection reliability while maintaining the lightweight, wire-free design.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

2Length of stationary object

If semiconductor chips are stacked vertically without gold wires, then thickness is reduced, but electrical connection reliability deteriorates due to potential damages when connecting upper and lower chips

Engineering Contradiction:

Improvethickness of semiconductor packageVSAvoidelectrical connection reliability

Core Design Contradiction:

Length of stationary objectVSReliability

Solution Approach 1:

The connection interface is segmented into a recess region in the upper chip and a bump on the lower chip. This segmentation enables a compact, thin design while ensuring reliable electrical connection through the interlocking bump-recess structure that prevents mechanical damage.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The bump structure is nested into the recess region, creating a compact connection that reduces overall package thickness. The nested configuration ensures mechanical protection of the electrical connection while minimizing the vertical space required, thereby reducing package thickness without compromising reliability.

Inventive Principle:

Principle #7Nested doll (Nesting)

3Area of stationary object

If small-sized bumps are used for connecting stacked semiconductor devices, then package size is reduced, but connection reliability deteriorates due to potential damages during connection

Engineering Contradiction:

Improvepackage sizeVSAvoidconnection reliability

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The small-sized bump is nested into a pre-formed recess region in the upper semiconductor chip. This nesting configuration protects the small bump from mechanical damage during connection while maintaining the compact package size. The recess acts as a protective cavity that secures the small bump in place.

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

The recess region is formed beforehand in the upper semiconductor chip to provide cushioning protection for the small-sized bump. This pre-prepared recess structure prevents damage to the small bump during the stacking and connection process, thereby maintaining connection reliability despite the small size of the bump and the resulting compact package.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS7851256B2Method of manufacturing chip-on-chip semiconductor device

Publication Date: 2010.12.14 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided is a method of fabricating a chip-on-chip (COC) semiconductor device. The method of fabricating a chip-on-chip (COC) semiconductor device may include preparing a first semiconductor device with a metal wiring having at least one discontinuous spot formed therein, preparing a second semiconductor device with at least one bump formed on a surface of the second semiconductor device corresponding to the at least one discontinuous spot, aligning the first semiconductor device onto the second semiconductor device, and connecting the at least one bump of the second semiconductor device to the at least one discontinuous spot formed in the metal wiring of the first semiconductor device.