Chip-on-wafer structures with polymer-filled trenches for die sawing stress management
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Solution Overview
Problem
The mechanical stress from die sawing through low-k dielectric materials in three-dimensional integrated circuit (3DIC) formation processes can cause cracks, leading to yield loss due to the propagation of cracks from the wafer to the chips.
Innovation Solution
The method involves forming trenches in scribe lines, filling them with a polymer, and using dielectric patterns to absorb stress, along with a backside grinding and CMP process to expose TSVs, and forming conductive features and dielectric patterns to reduce mechanical stress during the die sawing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a blade is used to saw the wafer and device dies into packages, then chip separation is achieved, but mechanical stress causes cracks in low-k dielectric materials leading to yield loss
Solution Approach 1:
The method performs preliminary actions before die sawing by forming trenches in scribe lines, filling them with polymer material, and creating stress-absorbing dielectric patterns. These preparatory steps are designed to prevent cracks before the mechanical stress of sawing occurs, thereby maintaining high yield rates while enabling efficient chip separation.
Solution Approach 2:
The patent applies beforehand cushioning by placing polymer-filled trenches and stress-absorbing dielectric patterns in strategic locations before the die sawing process. These structures act as cushioning elements that absorb mechanical stress during blade cutting, preventing stress transmission to the low-k dielectric materials and avoiding crack formation that would reduce yield.
2Ease of operation
If mechanical stress is applied during die sawing, then chip separation is achieved, but cracks propagate from the wafer to the chips
Solution Approach 1:
The patent introduces intermediary structures - polymer-filled trenches and stress-absorbing dielectric patterns - that act as mediators between the mechanical blade and the low-k dielectric materials. These intermediaries absorb and distribute mechanical stress, preventing direct stress transmission to the dielectric layers and blocking crack propagation paths from the wafer to the chips.
Solution Approach 2:
The method extracts or removes the harmful stress concentration points by creating trenches in the scribe lines and filling them with compliant polymer material. This extraction of stress concentration zones prevents the initiation and propagation of cracks during the mechanical sawing process, allowing easy chip separation without damage.
3Reliability
If low-k dielectric materials are used in the wafer, then electrical performance is improved, but the materials are susceptible to mechanical stress and cracking
Solution Approach 1:
The patent applies local quality by creating localized stress-management structures (polymer-filled trenches and stress-absorbing dielectric patterns) specifically in the scribe line regions where mechanical stress concentrates during sawing. The low-k dielectric materials are maintained in the chip areas for optimal electrical performance, while the scribe lines have modified local properties to handle mechanical stress, thus resolving the contradiction between electrical performance and mechanical strength.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes mechanical stress and prevents cracks in low-k dielectric materials, thereby reducing yield loss and ensuring reliable chip separation without damaging the polymer or conductive features.
Implementation Method 1
using dielectric patterns to absorb stress
Implementation Method 2
The mechanical stress applied by the blade may cause cracks
Data Source
AI summary
A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level.