Chip Design Verification for OTP Autoload Readback
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Solution Overview
Problem
The complexity of chip verification, particularly for one-time programmable (OTP) modules, necessitates a more accurate and comprehensive verification method to ensure normal operation and functionality, as these modules cannot be modified after initial programming.
Innovation Solution
A chip design verification system and method that includes an agent module, driver module, sequencer module, and result verification module to generate and compare test data sets with readout values, ensuring the autoload and re-autoload functions of OTP modules are functioning correctly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional verification methods are used for OTP modules, then verification coverage is limited, but verification accuracy and completeness deteriorate
Solution Approach 1:
The verification system is segmented into distinct functional modules: agent module (containing driver and sequencer), result verification module, and testbench. This segmentation allows each module to have specialized functions, improving verification accuracy while managing complexity through modular organization. The driver module handles data generation and writing, the sequencer controls test sequences, and the result verification module performs comparisons, ensuring comprehensive coverage without overwhelming system complexity.
Solution Approach 2:
The agent module acts as an intermediary between the testbench and the OTP module under test. It contains the driver module that generates test data and the sequencer that coordinates test sequences, serving as a mediator that translates verification requirements into concrete test operations. This intermediary structure improves verification completeness by providing a dedicated layer that specializes in OTP-specific test patterns while maintaining a clean interface with the rest of the verification system.
2Reliability
If comprehensive test functions are added to OTP modules, then chip operation accuracy improves, but design complexity increases
Solution Approach 1:
The verification system implements a universal testbench structure that can verify multiple OTP module functions through a unified framework. The agent module and result verification module are designed to handle various test scenarios (autoload, re-autoload, data writing, reading) through standardized interfaces and procedures. This multi-functional approach allows comprehensive verification of chip operation accuracy without requiring separate complex verification systems for each function, thereby managing design complexity while improving reliability.
Solution Approach 2:
The result verification module implements feedback by comparing actual readout values from the OTP module with expected test data, and reporting verification results. This feedback mechanism ensures that comprehensive test functions are properly validated, improving chip operation accuracy by detecting design errors. The feedback loop allows the verification system to adapt and confirm that each added test function operates correctly, managing the complexity of comprehensive testing through systematic validation.
3Measurement precision
If more test data sets are generated, then verification coverage increases, but verification time increases
Solution Approach 1:
The driver module generates and prepares test data sets in advance before actual verification execution. Test data including location information and data values are pre-configured and stored, allowing the sequencer to efficiently execute test sequences without real-time data generation overhead. This preliminary action increases verification coverage by enabling comprehensive test scenarios while reducing verification time by eliminating runtime data preparation delays.
Solution Approach 2:
The verification system maintains continuous useful action by implementing an efficient test flow where the sequencer continuously coordinates between the driver module and result verification module. Test sequences are designed to minimize idle time, with data writing, reading, and verification operations performed in a continuous manner. This continuity ensures that comprehensive test data sets are processed efficiently, increasing verification coverage without proportionally increasing verification time through optimized operational flow.
Data Source
AI summary
A chip design verification system and method, and a computer readable recording medium with a stored program are provided for verifying a module under test. The chip design verification system is configured to: transmitting, by the driver module, the test data sets to the result verification module and performing, by the driver module, a write procedure to write the test data sets into the storage space modules; performing, by the module under test, an autoload function to load the test data sets stored in the storage space modules into the registers correspondingly; and reading, by the result verification module, a plurality of first readout values corresponding to the test data sets at the registers according to the location data of each of the test data sets and comparing, by the result verification module, the test data sets with the first readout values to determine whether the autoload function operates normally.