Chip-on-Chip Output Pad Layout for Probe Test Access
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Solution Overview
Problem
The chip-on-chip package technology for semiconductor ICs limits probe test capabilities due to small bump pad sizes, requiring separate larger probe test pads, which increases chip area and production costs.
Innovation Solution
A semiconductor IC with a chip-on-chip structure that includes first and second bump pads, a probe test pad, and a pipe latch unit that selectively transfers data to either the bump pads or the probe test pad based on operating mode, optimizing pad arrangement for efficient testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If chip-on-chip package technology is used to stack control semiconductor IC and main semiconductor IC vertically, then operating frequency increases and total power consumption reduces, but bump pad size becomes too small (30-μm×30-μm) to properly perform probe test
Solution Approach 1:
The patent divides the testing function by separating the data output paths: one path goes to bump pads for normal operation, another path routes data through a pipe latch unit to dedicated probe test pads. This segmentation allows the small bump pads to maintain their high-speed function while larger probe test pads handle testing requirements independently.
Solution Approach 2:
The pipe latch unit acts as an intermediary component that receives data from the main semiconductor IC and selectively transfers it to either bump pads or probe test pads based on operational mode. This intermediary enables the system to switch between normal operation and test mode, resolving the contradiction between small pad size and testability.
2Ease of operation
If separate probe test pads are provided to enable normal probe test, then probe test capability is achieved, but chip area increases and production costs increase
Solution Approach 1:
The probe test pads serve multiple functions: they enable comprehensive probe testing of the main semiconductor IC while coexisting with the bump pad array for normal operation. The pipe latch unit provides multi-functionality by routing data to different destinations based on mode, making the test infrastructure more efficient and reducing overall area requirements.
Solution Approach 2:
The patent utilizes the vertical stacking dimension inherent in chip-on-chip architecture to accommodate both bump pads and probe test pads in different spatial planes. The pipe latch unit is positioned in the vertical stack to route signals, allowing horizontal space optimization while maintaining both high-speed data paths and test access paths.
3Speed
If bump pad size is reduced for high-speed signal transmission, then operating frequency increases, but the bump pads cannot properly perform probe test
Solution Approach 1:
The patent segments the data output function into two distinct pathways: one for high-speed operation through minimized bump pads, and another for testing through the pipe latch unit to larger probe test pads. This segmentation allows each component to be optimized for its specific function without compromise.
Solution Approach 2:
The probe test pads serve as functional copies or alternatives to the bump pads for testing purposes. Instead of requiring the bump pads themselves to be large enough for probing, the system creates dedicated probe test pads that replicate the data output function during test mode, allowing small bump pads to maintain their high-speed characteristics.
Data Source
AI summary
A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.