Chip-Overlap Reinforcement in Semiconductor Packages Against Warpage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization and slimming of semiconductor packages lead to deteriorated warpage characteristics, causing stress transmission to chips, which results in physical and electrical reliability issues and operational characteristic deterioration.
Innovation Solution
A semiconductor package design featuring an insulating layer with a reinforcement part that overlaps the chip vertically, differing electrode and through electrode sizes and thicknesses to enhance rigidity and prevent warpage, ensuring improved physical and electrical reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the package substrate is miniaturized and slimmed down to arrange electrodes in limited space, then the mounting area is reduced and integration is improved, but the warpage characteristics are deteriorated
Solution Approach 1:
The patent applies local quality by providing a reinforcement part with a specific modulus of elasticity only in the region vertically overlapping the chip, rather than uniformly throughout the entire package substrate. This localized reinforcement maintains the overall miniaturized and slimmed structure while specifically addressing the warpage issue in the critical chip region.
Solution Approach 2:
The patent uses composite materials by combining the insulating layer with a reinforcement part having different mechanical properties (higher modulus of elasticity). This composite structure allows the substrate to maintain both its slimmed-down form factor and sufficient rigidity to prevent warpage in the chip region.
2Area of stationary object
If the package substrate is miniaturized and slimmed down, then the mounting area is reduced, but stress is transmitted to the chip causing physical and electrical reliability problems
Solution Approach 1:
The reinforcement part is specifically positioned in the region vertically overlapping the chip to provide localized stress protection. This allows the rest of the package to remain miniaturized while the critical chip region is protected from stress that would cause reliability issues.
Solution Approach 2:
The reinforcement part acts as a pre-positioned protective element that prevents stress transmission to the chip before stress events occur. By having this reinforcement structure in place beforehand, the chip is protected from potential stress-induced reliability failures.
3Area of stationary object
If the package substrate is miniaturized and slimmed down, then the mounting area is reduced, but the operational characteristics of the chip are deteriorated due to stress
Solution Approach 1:
The reinforcement part is strategically placed only in the region vertically overlapping the chip, providing localized protection that preserves chip operational characteristics without affecting the overall miniaturized package structure.
Data Source
AI summary
A semiconductor package according to an embodiment includes an insulating layer; a first electrode part disposed on the insulating layer; a through electrode passing through the insulating layer and electrically connected to the first electrode part; and a reinforcement part disposed in the insulating layer; a connection part disposed on the first electrode part; and a chip mounted on the connection part, and wherein at least a portion of the reinforcement part vertically overlaps the chip and is not connected to the through electrode.