Chip Package Alignment Marks for Accurate Redistribution Layer Bonding
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Solution Overview
Problem
Current manufacturing methods for electronic devices face challenges in achieving accurate alignment between electronic elements and circuits, leading to electrical defects and reliability issues.
Innovation Solution
A manufacturing method involving the formation of an intermediate layer with alignment marks, a release layer, and an insulating layer to create a package structure with a step difference between the chip surface and the insulating layer, allowing for improved alignment accuracy and electrical connectivity through a redistribution layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional packaging and redistribution processes are used, then manufacturing is simplified, but alignment accuracy between electronic elements and circuits deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-forming alignment marks on the carrier before chip placement. These alignment marks serve as reference features that guide the positioning of electronic elements, ensuring accurate alignment is established early in the manufacturing process rather than relying on post-placement adjustments. This preliminary structuring of alignment information directly improves manufacturing precision while maintaining process simplicity.
Solution Approach 2:
The patent introduces an intermediate carrier structure that acts as a mediator between the chip placement process and the final circuit assembly. The carrier includes intermediate layers with alignment marks that facilitate precise positioning without requiring complex direct alignment mechanisms. This intermediary carrier simplifies the overall process while achieving high alignment accuracy through its structured reference features.
2Reliability
If alignment accuracy is improved through complex processes, then electrical defects are reduced, but manufacturing cost increases
Solution Approach 1:
The intermediate carrier with integrated alignment marks serves as a cost-effective mediator that improves electrical reliability. Rather than implementing complex real-time alignment systems or multiple inspection steps, the patent uses this simple intermediary structure with pre-formed alignment marks to ensure accurate positioning, thereby reducing electrical defects without significantly increasing manufacturing cost.
Solution Approach 2:
By pre-forming alignment marks on the carrier before chip placement, the patent establishes accurate alignment early in the process. This preliminary action prevents misalignment-related electrical defects without requiring expensive post-placement correction systems or complex alignment equipment, thus maintaining ease of manufacture while improving reliability.
3Productivity
If misalignment occurs between circuits and electronic elements, then manufacturing is simpler, but electrical defects increase
Solution Approach 1:
The patent maintains manufacturing efficiency by using a simple carrier-based placement process, but improves electrical functionality through preliminary formation of alignment marks on the carrier. These pre-established reference features enable accurate positioning of electronic elements without slowing down the manufacturing process, thus preventing misalignment-related electrical defects while preserving productivity.
Solution Approach 2:
The intermediate carrier structure acts as a mediator that reconciles the conflict between simple manufacturing and electrical reliability. The carrier with its integrated alignment marks provides a straightforward placement process that inherently ensures accurate alignment, eliminating the need for complex alignment procedures that would reduce productivity while still preventing electrical defects.
Data Source
AI summary
A manufacturing method of an electronic device and an electronic device are disclosed. The method includes: forming an intermediate layer on a first carrier, patterning the intermediate layer to form alignment marks; forming a release layer on the first carrier; disposing chips on the release layer, each chip including a bonding pad and a surface; forming an insulating layer surrounding the chips on the release layer to form a package structure; transferring the package structure to a second carrier, enabling the surface of each chip to face away from the second carrier and to be exposed by an upper surface of the insulating layer, a step difference formed between the surface of each chip and at least a portion of the upper surface of the insulating layer in a normal direction; and forming a redistribution layer electrically connected to each chip through the bonding pads on the package structure.