Chip Package Alignment Marks for Precise Dicing
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Solution Overview
Problem
The shrinking size of chips and increasing number of pads make it difficult to form accurate wires in chip packages, and the dicing process is affected by the accuracy of alignment marks, leading to reliability and performance issues.
Innovation Solution
A chip package is formed with a semiconductor substrate, dielectric layer, conducting pads, and alignment marks extending from the second surface to the first surface, allowing for precise dicing along predetermined scribing lines using the alignment marks to ensure accurate separation and prevent damage to the die region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the chip size is shrunk and the number of pads is increased, then the integration density is improved, but the difficulty of forming accurate wires increases
Solution Approach 1:
Alignment marks are formed in the substrate before the dicing process, extending from the second surface toward the first surface. These pre-formed marks serve as reference points that guide the dicing blade during subsequent processing, enabling precise separation of chips even as chip size shrinks and pad density increases.
2Reliability
If the dicing process accuracy is improved, then the reliability of chip packages is improved, but the complexity of alignment mark formation increases
Solution Approach 1:
The alignment mark formation process is segmented into distinct steps: first forming marks that extend from the second surface toward the first surface, then selectively removing portions of the substrate. This segmentation allows each step to be optimized independently, improving dicing accuracy without overwhelming process complexity.
Solution Approach 2:
Alignment marks are formed by extending structures from the second surface toward the first surface, utilizing the vertical dimension of the substrate. This three-dimensional approach to alignment mark formation provides robust reference points for dicing while maintaining compatibility with standard planar processing techniques.
3Manufacturing precision
If alignment marks are used for dicing, then the accuracy of chip separation is improved, but the substrate structure becomes more complex
Solution Approach 1:
Only portions of the substrate are removed to form alignment marks, rather than modifying the entire substrate structure. The marks extend from the second surface toward the first surface but do not require complete through-hole formation, providing sufficient alignment functionality while minimizing structural complexity and material removal.
Data Source
AI summary
An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface.