Chip Package Antenna Pattern Surface Roughness
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Solution Overview
Problem
The demand for smaller and more advanced packaging techniques for semiconductor devices, particularly for high-performance applications with integrated antennas, is not adequately met by existing methods, which struggle to efficiently integrate and test 3D packaging and 3DIC devices.
Innovation Solution
A manufacturing method involving the formation of redistribution structures with interlayer vias and the integration of antenna patterns on insulating layers, using materials like polybenzoxazole and conductive powders, to create efficient chip packages with embedded antennas, allowing for low-loss signal transmission and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wafer-level packaging is used to shrink device size, then device miniaturization is achieved, but integration of high-performance antennas and 3D packaging becomes more difficult
Solution Approach 1:
The patent segments the antenna structure into multiple components: a bottom electrode layer, an insulating layer with through-holes, and a top electrode layer. This segmentation allows each layer to be processed and integrated separately at the wafer level, reducing overall integration complexity while enabling device miniaturization.
Solution Approach 2:
The patent transitions from planar antenna designs to three-dimensional stacked architectures by introducing vertical through-holes and multiple electrode layers. This dimensional change enables higher integration density and performance within a smaller footprint, resolving the contradiction between size reduction and integration complexity.
2Ease of manufacture
If conventional packaging methods are used, then manufacturing process is simpler, but signal transmission loss increases and bandwidth performance decreases
Solution Approach 1:
The patent changes the dielectric parameters by using insulating layers with controlled permittivity and loss tangent values. By optimizing these material parameters and the geometric parameters of through-holes, the design achieves low signal transmission loss while maintaining manufacturability through standard wafer-level processing techniques.
3Reliability
If 3D packaging and 3DIC devices are integrated, then performance and bandwidth are improved, but manufacturing complexity and testing difficulty increase
Solution Approach 1:
The patent performs preliminary integration of antenna structures with semiconductor devices at the wafer level before final packaging. Through-holes are formed and electrodes are connected in advance, allowing 3D packaging and 3DIC integration to proceed with reduced complexity and enabling more straightforward testing of the complete assembled device.
Data Source
AI summary
An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, an antenna pattern, and an insulating layer. The chip package includes a semiconductor die and an insulating encapsulation enclosing the semiconductor die. The antenna pattern is electrically coupled to the chip package, where a material of the antenna pattern comprises a conductive powder having fused metal particles. The insulating layer disposed between the chip package and the antenna pattern, where the antenna pattern includes a first surface in contact with the insulating layer, and a second surface opposite to the first surface, and a surface roughness of the second surface is greater than a surface roughness of the first surface.