Semiconductor Chip Package Array Groove Design
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Solution Overview
Problem
The soldering performance of semiconductor chip package devices is undesirable due to the limited area available for soldering, as the distance between adjacent pins decreases and pin density increases, making it challenging to achieve reliable soldering.
Innovation Solution
A semiconductor chip package array is designed with a lead frame featuring first, second, and third grooves that form through holes and connect to support units, an encapsulating layer covering the chips and support units, and an electroplating layer extending into these grooves, increasing the soldering area and improving soldering performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pin density is increased and the distance between adjacent pins is decreased, then the semiconductor chip package device achieves high density and high performance, but the soldering performance becomes undesirable due to limited soldering area
Solution Approach 1:
The patent transitions from a traditional flat pin structure to a three-dimensional pin structure by forming grooves on the pin surface. This dimensional change creates additional surfaces (side walls and bottom of grooves) that provide extra soldering area, effectively resolving the contradiction between high pin density and adequate soldering area.
Solution Approach 2:
The patent applies local quality by creating grooves with specific characteristics (depth, width, shape) at specific locations on the pin surface. This localized structural modification concentrates the soldering area enhancement where most needed, while maintaining the overall high-density pin arrangement.
2Volume of moving object
If the size of the semiconductor chip package device is decreased, then the device achieves high density, but the soldering area becomes limited
Solution Approach 1:
By forming grooves on the pin surface, the patent effectively increases the soldering area without increasing the overall device footprint. The groove structures utilize the vertical dimension and surface area of existing pins, providing additional soldering real estate within the same device size constraints.
Solution Approach 2:
The groove structures are nested within or on the surface of the pins themselves, rather than adding external components. This nesting approach increases soldering area while maintaining compact device dimensions, as the additional soldering surfaces are integrated into the existing pin geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced design increases the soldering area and improves soldering performance by providing additional surfaces for solder to climb, resulting in better production ratios and reliability of semiconductor chip package devices.
Implementation Method 1
an electroplating layer extending into the third grooves or into the third grooves and the second grooves
Data Source
AI summary
Semiconductor chip package array is provided. The semiconductor chip package array includes: a lead frame, chips, an encapsulating layer, and an electroplating layer. The lead frame includes a first surface, a second surface, a plurality of support units arranged in a matrix, first grooves, second grooves, and third grooves. The first grooves are connected to the second grooves to form through holes and the third grooves are connected to adjacent support units of the plurality of support units. The chips are disposed on and electrically connected to the plurality of support units. An encapsulating material encapsulates the chips and at least a portion of the plurality of support units, and fill the first grooves to form the encapsulating layer. The electroplating layer is disposed on the second surface of the lead frame, and extends into the third grooves or into the third grooves and the second grooves.