Chip Package With Backend Side Interconnects And TSV Redundancy
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Solution Overview
Problem
Conventional 3D chip packages with through silicon vias (TSVs) face reliability issues due to thermal stresses causing deformation and electrical connection failures, with existing designs not maximizing surface area or accounting for TSV failures effectively.
Innovation Solution
The implementation of a chip package with backend side interconnects and optional vertical TSVs, along with a network organizer that manages communications and identifies TSV failures, providing redundancy and load balancing to enhance reliability and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If TSV technology is used to create vertical connections through chips, then packaging size is reduced and electrical paths are shortened, but thermal stresses cause chip deformation and TSV connection failure
Solution Approach 1:
The patent introduces a compliance layer between the chip and TSV structure that can deform elastically under thermal stress. This compliance layer acts as a cushion that absorbs thermal expansion differences between dissimilar materials (e.g., silicon chip and metal interconnects), preventing stress concentration at the TSV connections before failure can occur. The layer is designed with specific mechanical properties to accommodate thermal cycling without compromising electrical connectivity.
Solution Approach 2:
The patent employs composite material structures in the TSV formation process, using combinations of materials with complementary properties. For example, multi-layer dielectric structures with different thermal expansion coefficients are used to create a gradient that reduces stress concentration. The interconnect structure itself may use composite materials such as copper TSVs with tungsten plugs or coated structures to optimize both electrical performance and thermal stress resistance.
2Reliability
If conventional edge wiring is used to wire chips together, then electrical connections are established, but package length and width increase and interposer layers are required
Solution Approach 1:
The patent transitions from conventional 2D edge wiring to 3D vertical TSV connections. By utilizing the vertical dimension through the chip thickness, the interconnect structure achieves shorter electrical paths without increasing the chip's footprint. Multiple TSVs can be arranged in a vertical stack, enabling three-dimensional integration that dramatically reduces the required package area while maintaining or improving electrical connection reliability through direct vertical pathways.
Solution Approach 2:
The patent eliminates the need for separate interposer layers by integrating the TSV structures directly into the chip substrate. The TSVs are formed by removing material (drilling or etching holes) through the chip and then filling them with conductive material, thereby extracting the interconnection function from a separate interposer component and embedding it within the chip structure itself. This reduces the total package layers and simplifies the overall structure.
3Productivity
If maximum surface area is utilized for interconnections, then more connections are possible, but thermal stress concentration increases leading to higher failure rates
Solution Approach 1:
The patent applies local quality by varying the density and distribution of TSVs across different regions of the chip based on local requirements. Areas with high signal integrity requirements or sensitive to thermal stress may have reduced TSV density or enhanced protective structures, while areas requiring high bandwidth can have higher density. The compliance layer and stress management structures are strategically placed in regions where thermal stress concentration is most likely to occur, providing localized protection without sacrificing overall interconnection density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maximizes surface area usage, increases reliability, and improves chip package yield by enabling efficient communication and redundancy management, balancing data load and handling TSV performance variations.
Implementation Method 1
a compliance layer comprising a first material different than the semiconductor material of the semiconductor chip, the compliance layer disposed between the semiconductor chip and the set of TSVs, wherein the compliance layer is configured to deform to reduce stress concentration at the set of TSVs
Data Source
AI summary
In general, embodiments of the present invention provide a chip package with multiple TSV configurations. Specifically, the chip package typically includes a backend layer (e.g., metal interconnect layer); a substrate coupled to the backend layer; a set (at least one) of backend side interconnects extending (e.g., angularly) from a side surface of the backend layer to a bottom surface of the backend layer; a set of optional vertical TSVs extending from a top surface of the backend layer through the substrate; and a network organizer positioned in the substrate organizer for handling communications made using the set of backend side interconnects and the set of vertical TSVs. A set of connections (e.g., controlled collapse chip connections (C4s) can be positioned adjacent to any of the vias to provide connectively to other hardware elements such as additional chip packages, buses, etc. Among other things, the use of backend side interconnects allows maximum surface area of the chip package to be utilized and provides increased reliability. These advantages are especially realized when used in conjunction with vertical TSVs.