Chip Package Layout With Integrated Device Beneath the Die
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Solution Overview
Problem
Existing semiconductor packaging techniques have limitations in achieving efficient integration and reduced size while maintaining signal and power integrity, particularly in 3D packaging and IC devices, where the scaling-down process does not fully address the need for smaller, more efficient chip packaging structures.
Innovation Solution
The development of a package structure that includes a redistribution substrate with laminated insulating layers and conductive features, where semiconductor chips are bonded to the substrate using flip-chip bonding and conductive structures, with integrated devices positioned beneath the chips to reduce routing length and enhance thermal management, allowing for smaller package sizes and improved electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to increase functional density, then production efficiency increases and costs decrease, but package size reduction and thermal management become more challenging
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional packaging by stacking semiconductor chips vertically on the substrate. Multiple chips are arranged in layers with conductive structures connecting them, utilizing the vertical dimension to increase functional density without proportionally increasing the package footprint area.
Solution Approach 2:
The patent implements a hierarchical nested structure where conductive structures are embedded within the substrate, chips are mounted on the substrate, and additional conductive structures are formed between chips. This nested arrangement optimizes space utilization and enables compact packaging while maintaining electrical connectivity.
2Area of stationary object
If chips are closely integrated to reduce package size, then area utilization improves, but signal integrity and power delivery become more difficult to maintain
Solution Approach 1:
The patent introduces conductive structures as intermediary elements between the substrate and semiconductor chips, and between adjacent chips. These conductive structures serve as mediators for signal and power transmission, enabling reliable electrical connectivity despite the close integration and reduced package area.
Solution Approach 2:
The patent segments the electrical connection path into multiple sections through the use of conductive structures at different levels and positions. This segmentation allows for optimized signal routing and power distribution across the three-dimensional chip stack, maintaining signal integrity despite close integration.
3Length of moving object
If routing length is reduced by integrating devices beneath chips, then signal transmission improves, but manufacturing complexity increases
Solution Approach 1:
The patent forms conductive structures within the substrate before mounting the semiconductor chips. This preliminary action establishes the electrical connection pathways in advance, allowing for reduced routing length and simplified subsequent chip mounting and interconnection processes.
Solution Approach 2:
The patent moves conductive structures into the vertical dimension by forming them at different depths within the substrate and between chip layers. This three-dimensional arrangement of conductive structures reduces the horizontal routing length while the manufacturing process remains manageable through sequential formation steps.
Data Source
AI summary
A package structure and a method of forming the same are provided. The package structure includes a package substrate, a semiconductor chip disposed over the package substrate, and an integrated device located below and bonded to the lower surface of the semiconductor chip. The semiconductor chip has a lower surface facing the package substrate and is electrically connected to the package substrate through conductive structures. The integrated device is laterally surrounded by the conductive structures, and the integrated device and the conductive structures are located within boundaries of the semiconductor chip when viewed in a direction perpendicular to the lower surface of the semiconductor chip.