Chip Package Bridge Portions for Uniform Thermal Conduction
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Solution Overview
Problem
The chip packaging process faces issues with non-uniform oxide layer formation due to vacuum gaps between the carrier wafer and deposition equipment pins, leading to poor thermal conduction and quality of chip packages.
Innovation Solution
A method involving a second substrate with rectangular chip regions separated by a scribed-line region, where portions corresponding to the scribed-line region are removed to form chips with bridge portions between adjacent chips, enhancing thermal conduction and uniformity of the insulating layer during deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the carrier wafer is supported on pins during deposition, then the deposition process can be performed, but vacuum gaps are formed between the carrier wafer and pins, leading to poor thermal conduction
Solution Approach 1:
The carrier wafer is segmented into multiple individual chip carriers, each capable of independent contact with the deposition surface. This segmentation eliminates the vacuum gap problem by ensuring each chip has direct thermal contact with the deposition equipment surface, while still allowing the deposition process to proceed uniformly across all chips.
Solution Approach 2:
The invention transitions from a two-dimensional planar contact problem to a three-dimensional solution by using protruding portions that extend downward from the chip carriers. These protrusions make contact with the deposition surface at a lower level, creating a vertical dimension for thermal contact that bypasses the vacuum gap issue while maintaining the deposition process capability.
2Force
If vacuum gaps exist between carrier wafer portions and pins, then the carrier wafer can be supported, but thermal conduction during deposition becomes poor
Solution Approach 1:
The invention introduces bridge portions as intermediary structures that connect adjacent chip carriers. These bridge portions provide both mechanical support and thermal conduction pathways, acting as mediators that transfer thermal energy between chips while maintaining structural integrity during the deposition process.
Solution Approach 2:
The protruding portions and bridge portions are formed in advance during the carrier wafer fabrication process, before the deposition occurs. This preliminary structuring ensures that thermal contact pathways are already established and optimized for the upcoming deposition process, preventing thermal conduction issues from the outset.
3Productivity
If poor thermal conduction occurs during deposition, then the process can continue, but the oxide layer thickness becomes non-uniform
Solution Approach 1:
The invention applies local quality enhancement by providing direct thermal contact specifically at the chip locations through protruding portions, while the bridge portions provide localized thermal pathways between adjacent chips. This localized thermal enhancement ensures uniform oxide layer formation precisely where needed, without compromising overall deposition process continuity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eliminates vacuum gaps, ensuring great and uniform thermal conduction between chips, resulting in improved quality and uniformity of the chip packages by forming bridge portions that connect adjacent chips, thus preventing non-uniform oxide layer thickness.
Implementation Method 1
the portions of the carrier wafer previously supported by the pins are not in contact with the work surface of the equipment. Therefore, the overlying chips adjacent to the vacuum gaps have poor thermal conduction during the deposition process
Data Source
AI summary
A method for forming a chip package is provided. A first substrate is provided. A second substrate is attached on the first substrate, wherein the second substrate has a plurality of rectangular chip regions separated by a scribed-line region. A portion of the second substrate corresponding to the scribed-line region is removed to form a plurality of chips on the first substrate, wherein at least one bridge portion is formed between adjacent chips. A chip package formed by the method is also provided.