Chip Package Structure for Ultra-Thin Bridge Chip Reliability
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Solution Overview
Problem
Conventional fan-out package structures with bridge chips are prone to breaking during grinding and mounting due to their limited thickness, affecting product yield and reliability when attached to a PI layer using die adhesive.
Innovation Solution
A chip package structure where chips are flip-chipped onto a metal wiring layer without initial grinding, followed by grinding after flip-chip and molding, with a second chip acting as a bridge to reduce thickness and design height, and using a bottom filler for enhanced reliability, and including an insulation layer for the second metal pillar.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the bridge chip is thinned before mounting, then the thickness of the chip package structure is reduced, but the chip becomes too thin and is easily broken during grinding and mounting
Solution Approach 1:
The chip is mounted on the metal wiring layer before grinding. This preliminary mounting action allows the chip to be supported by the molding layer during subsequent grinding, preventing the chip from breaking even when ground to extreme thinness. The sequence is reversed from conventional approaches where grinding precedes mounting.
Solution Approach 2:
The molding layer is formed to cover the chip before grinding, providing mechanical support and cushioning to the chip during the grinding process. This beforehand cushioning prevents the thin chip from breaking under the stress of grinding and mounting operations.
2Ease of manufacture
If the chip is mounted using die adhesive on PI layer, then the mounting process is simple, but the reliability of the attached product cannot be guaranteed
Solution Approach 1:
The invention changes the mounting method from die adhesive bonding to flip-chip soldering. This parameter change in the bonding mechanism provides both mechanical interlocking and metallurgical bonding, significantly improving reliability while maintaining manufacturing feasibility through automated reflow soldering processes.
Solution Approach 2:
The invention uses a composite bonding approach combining solder material with metallization layers on both the chip and metal wiring layer. This composite material system provides superior bonding strength and reliability compared to single-material die adhesive bonding.
3Length of stationary object
If the second chip is made extremely thin, then the overall package thickness is reduced, but the electroplating process becomes more difficult
Solution Approach 1:
The metal wiring layer with metal pillars is prepared in advance before the second chip is mounted. This preliminary preparation of the substrate allows the electroplating process to be performed on a stable, thick metal wiring layer rather than on the thin chip itself, making the electroplating process easier and more reliable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach ensures the chips are as thin as possible without breaking, reducing the entire package thickness, improving reliability, and simplifying the electroplating process for the metal pillars, while enhancing the structural firmness and reliability of the package.
Implementation Method 1
the chip is bonded on the metal wiring layer through solder
Implementation Method 2
a filler is provided between the front surface of the first chip and the metal wiring layer
Data Source
AI summary
The present disclosure discloses a chip package structure and a preparation method thereof. The chip package structure includes: a metal wiring layer; a first chip, wherein a front surface of the first chip is flip-chipped on a first surface of the metal wiring layer; a first molding layer coating the first chip; a second chip, wherein a front surface of the second chip is flip-chipped on a second surface of the metal wiring layer; a first metal pillar formed on the second surface of the metal wiring layer; a second molding layer coating the second chip and the first metal pillar; and a second metal pillar formed on one side that is of the second molding layer and that is far away from the metal wiring layer, wherein the second metal pillar is at least partially connected to the corresponding first metal pillar.