Chip Package Buffer Plug Prevents Via Delamination

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Solution Overview

Problem

Through-silicon vias in chip device packages often delaminate during thermal cycle tests, reducing the reliability of packaged chips due to the delamination of the redistribution layer from the sidewall of the vias.

Innovation Solution

A chip device package design that includes a semiconductor substrate with a conductive trace layer extending to through holes, a buffer plug with reduced adhesion to the protection layer, and a protection layer covering the substrate, which helps prevent delamination by offsetting thermal expansion differences and pull-up forces during thermal cycles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If through-silicon vias are used to reduce package size, then the size of chip device packages is reduced, but the redistribution layer delaminates from the sidewall of the vias during thermal cycle tests

Engineering Contradiction:
Improvepackage sizeVSAvoiddelamination resistance
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

A buffer plug is introduced as an intermediary layer between the conductive trace layer and the protection layer within the through-silicon via. This buffer plug acts as a stress-absorbing mediator that prevents direct stress transmission between the protection layer and conductive trace layer during thermal cycling, thereby eliminating delamination while maintaining the via structure's integrity and the package's compact size.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The adhesion strength between layers is modified by changing material parameters. The buffer plug is specifically designed with reduced adhesion to the protection layer compared to traditional direct bonding structures. This parameter change allows the buffer plug to slip relative to the protection layer during thermal expansion, absorbing stress and preventing delamination of the conductive trace layer.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the protection layer is made more adherent to prevent delamination, then delamination is prevented, but thermal expansion differences cause increased stress and potential failure

Engineering Contradiction:
Improvedelamination resistanceVSAvoidthermal stress
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

The adhesion strength between layers is modified by changing material parameters. The buffer plug is specifically designed with reduced adhesion to the protection layer compared to traditional direct bonding structures. This parameter change allows the buffer plug to slip relative to the protection layer during thermal expansion, absorbing stress and preventing delamination of the conductive trace layer.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The buffer plug serves as a stress-absorbing intermediary that decouples the thermal expansion between the protection layer and conductive trace layer. By having controlled reduced adhesion to the protection layer, the buffer plug can move independently to accommodate thermal expansion differences, significantly reducing thermal stress transmission while still preventing delamination.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances the reliability of chip device packages by preventing delamination and maintaining structural integrity during thermal tests, ensuring the package's durability and performance.

Implementation Method 1

a buffer plug with reduced adhesion to the protection layer, and a protection layer covering the substrate, which helps prevent delamination by offsetting thermal expansion differences

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS9196571B2Chip device packages and fabrication methods thereof
Publication Date: 2015.11.24 XINTEC INC
  • US9196571B2 patent drawing
  • US9196571B2 patent drawing
  • US9196571B2 patent drawing

AI summary

A chip device package and a fabrication method thereof are provided. The chip device package includes a semiconductor substrate having a first surface and an opposing second surface. A recessed portion is disposed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the second surface of the semiconductor substrate. A protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion. A through hole is disposed on the first surface of the semiconductor substrate. A buffer material that is different from the material of the protection layer is disposed in the through hole and covered by the protection layer.