Chip Package Buffer Plug Prevents TSV Delamination
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Solution Overview
Problem
Through-silicon vias in chip packages are prone to delamination during thermal cycles due to the delamination of the redistribution layer from the sidewall, reducing the reliability of the packaged chips.
Innovation Solution
A chip package design and fabrication method that includes a semiconductor substrate with through holes and a conductive trace layer, where a buffer plug with a specific coefficient of thermal expansion is used to separate the conductive trace layer and protection layer, and a protection layer is applied to cover the substrate, enhancing adhesion and preventing delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If through-silicon vias are used to reduce chip package size, then the chip package size is reduced, but the redistribution layer delaminates from the sidewall during thermal cycles
Solution Approach 1:
A buffer plug made of material with intermediate thermal expansion properties is inserted between the conductive trace layer and protection layer in the through-silicon via. This buffer plug acts as a mediator that absorbs thermal stress during temperature cycling, preventing the conductive trace layer from delaminating while maintaining the compact via structure
Solution Approach 2:
The patent changes the material parameters of the via fill structure by introducing a buffer plug with specific thermal expansion characteristics. This parameter modification allows the via structure to accommodate thermal cycling stresses without causing delamination, thus maintaining both compact size and reliability
2Reliability
If a buffer plug with tailored coefficient of thermal expansion is added to prevent delamination, then the reliability during thermal cycles is improved, but the device structure becomes more complex
Solution Approach 1:
The via structure is segmented into distinct functional layers: the conductive trace layer for electrical connection, the buffer plug for thermal stress management, and the protection layer for mechanical support. This segmentation allows each layer to perform its specific function optimally while maintaining overall structural integrity during thermal cycling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents delamination during thermal cycles, improving the reliability and durability of the chip packages by using a buffer plug with a tailored coefficient of thermal expansion to offset the expansion differences between the protection and insulating layers.
Implementation Method 1
a buffer plug with a specific coefficient of thermal expansion is used to separate the conductive trace layer and protection layer, and a protection layer is applied to cover the substrate, enhancing adhesion and preventing delamination
Data Source
AI summary
A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.