Chip Package Carrier Base Structure for Warp-Resistant TSV Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in packaging large chips is the insufficient support or rigidity, leading to warping or deformation, and increasing the difficulty of fabricating through-substrate via (TSV) electrodes.
Innovation Solution
A chip package design that includes a device substrate with through-via openings, a first redistribution layer, a carrier base, and conductive connection structures, which allows for the formation of TSVs without increasing the chip's thickness, thereby enhancing structural strength and reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the chip's thickness is increased to improve support and rigidity, then the structural strength is improved, but the difficulty of fabricating through-substrate via (TSV) electrodes increases
Solution Approach 1:
The patent introduces a carrier substrate as an additional dimensional layer beneath the chip, transferring the support function from increasing chip thickness to adding a separate structural layer. This dimensional change allows the chip to maintain its original thin profile while gaining rigidity through the carrier substrate, thereby avoiding the need to increase chip thickness and the associated TSV fabrication difficulties.
Solution Approach 2:
The patent segments the support function from the chip itself by introducing a separate carrier substrate. Instead of making the chip thicker to provide support, the support function is isolated to the carrier substrate layer, allowing the chip to remain thin while still achieving the required structural strength. This segmentation resolves the contradiction by assigning different functions to different layers.
2Stability of the object's composition
If the chip's thickness is increased to prevent warping or deformation, then the structural stability is improved, but the device complexity increases
Solution Approach 1:
The patent adds a carrier substrate dimension beneath the chip to provide structural stability, allowing the chip itself to remain thin and simple. The stability function is achieved in a separate dimensional layer, avoiding the need to increase chip thickness and the associated complexity of fabricating high aspect ratio TSVs through thicker substrates.
Solution Approach 2:
The carrier substrate acts as an intermediary layer between the chip and the packaging structure, providing the necessary structural stability and support. This intermediary layer absorbs the complexity of providing mechanical strength, allowing the chip to remain simple while achieving the required stability through the carrier substrate's presence.
Data Source
AI summary
A chip package is provided. The chip package includes a device substrate, a first redistribution layer (RDL), a carrier base, and at least one conductive connection structure. The device substrate has at least one first through-via opening extending from the backside surface of the device substrate to the active surface of the device substrate. The first RDL is disposed on the backside surface of the device substrate and extends in the first through-via opening. The carrier base carries the device substrate, and has a first surface facing the backside surface of the device substrate and a second surface opposite the first surface. The conductive connection structure is disposed on the second surface of the carrier base and is electrically connected to the first RDL.