Chip Package Manufacturing via Carrier Etching and Parallel Die Processing
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Solution Overview
Problem
The high cost and complexity of serial processes in semiconductor chip assembly, particularly in wire bonding and individual molding of chips, lead to increased expenses and logistical challenges due to the need for sequential processing of each die, which contributes significantly to the overall manufacturing costs.
Innovation Solution
A method for manufacturing chip packages where multiple dies are processed in parallel on a wafer, involving the formation of a carrier with multiple dies, separation between the dies by removing portions of the carrier, forming encapsulation material in these areas, and separating the dies through the encapsulation material, allowing for batch processing and reducing the need for individual handling and serial processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If serial processes are used for wire bonding and individual molding of chips, then each die can be processed individually with precise control, but manufacturing costs increase significantly and productivity decreases
Solution Approach 1:
The patent segments the manufacturing process into two distinct phases: a parallel processing phase where multiple dies are simultaneously bonded and molded while remaining on the wafer, and a final separation phase where individual chip packages are detached. This segmentation allows the system to achieve both high productivity during parallel processing and individual precision during the final separation and testing stages, resolving the contradiction between mass production efficiency and individual processing control.
2Ease of operation
If serial processes are used for wire bonding and individual molding of chips, then each die can be handled individually, but manufacturing complexity and costs increase significantly
Solution Approach 1:
The patent merges multiple individual operations into a single integrated process by performing wire bonding and molding for multiple dies simultaneously while they remain mounted on the wafer. This consolidation reduces the overall number of process steps, eliminates the need for repeated setup and handling between individual operations, and simplifies the manufacturing system while maintaining the ability to perform precise individual operations when needed.
3Ease of manufacture
If conventional mechanical sawing is used to separate dies, then individual chips can be obtained, but manufacturing costs increase and ultra-thin chip production becomes difficult
Solution Approach 1:
The patent replaces the conventional mechanical sawing process with a chemical etching process that uses selective removal of sacrificial oxide layers to separate individual chip packages from the wafer. This substitution eliminates the mechanical forces that limit ultra-thin chip production, enables lower manufacturing costs through batch processing, and maintains the ability to obtain individually separated chips. The chemical process can handle extremely thin substrates that would be damaged or destroyed by mechanical sawing.
Data Source
AI summary
A method for manufacturing a chip package is provided. The method including: holding a carrier including a plurality of dies; forming a separation between the plurality of dies by removing from the carrier one or more portions of the carrier between the plurality of dies; forming an encapsulation material in the removed one or more portions between the plurality of dies; separating the dies through the encapsulation material.