Chip Package With Integrated Heat Dissipation Chamber
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Solution Overview
Problem
Current chip packages face challenges with heat dissipation due to increasing integration density and circuit performance, leading to thermal overload, and existing cooling methods are inefficient and costly, with non-hermetic packages failing to protect against environmental factors like humidity and radiation.
Innovation Solution
A chip package design featuring a glass-based encapsulation structure with a passivation layer and electrically conductive layer, incorporating cavities for heat dissipation and a second encapsulation structure with inlet and outlet for controlled heat flow, integrated at the wafer level to simplify manufacturing and reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If increasing circuit integration density and performance, then circuit capability is improved, but thermal load increases leading to overheating
Solution Approach 1:
The patent merges the cooling function directly into the encapsulation structure by integrating a heat dissipation chamber and coolant flow paths within the package itself, combining protection and thermal management into a single integrated system rather than adding separate cooling components
Solution Approach 2:
The patent introduces a coolant as an intermediary substance that flows through the heat dissipation chamber to transfer heat away from the circuit components, enabling efficient heat removal without direct thermal contact between moving parts
2Temperature
If using conventional cooling methods with external cooling bodies, then heat dissipation is achieved, but efficiency is reduced due to insulation interfaces
Solution Approach 1:
The cooling function is merged directly into the encapsulation structure, eliminating the need for separate external cooling bodies and reducing thermal resistance by removing intermediate insulation interfaces between the circuit board and cooling components
Solution Approach 2:
The patent transitions from external/attached cooling to internal/integrated cooling by embedding the heat dissipation chamber within the encapsulation structure, moving the cooling function from a separate dimensional layer to an integrated three-dimensional structure
3Ease of manufacture
If using non-hermetic packages for cost reduction, then manufacturing cost decreases, but protection against environmental factors is insufficient
Solution Approach 1:
The patent uses a composite encapsulation structure combining glass or ceramic materials that provide both hermetic sealing for environmental protection and integrated cooling channels, achieving reliable protection while maintaining manufacturing feasibility through material composition rather than complex assembly
4Temperature
If thinning chip methods are used to reduce thermal mass, then thermal load is reduced, but manufacturing complexity increases
Solution Approach 1:
Instead of modifying the chip itself through complex thinning processes, the patent extracts the thermal management function to the encapsulation level by providing active cooling through the package structure, removing the need for complex chip preparation while maintaining thermal control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances thermal management, reduces manufacturing costs, and provides improved reliability and stability against environmental factors by integrating active cooling directly on the chip, minimizing thermal stress and moisture absorption.
Implementation Method 1
the inlet and the outlet control an inflow and outflow of heat dissipating material to and from the chamber region
Data Source
AI summary
A chip package is provided, the chip package including: first encapsulation structure; first passivation layer formed over first encapsulation structure and first electrically conductive layer formed over first passivation layer; at least one chip arranged over first electrically conductive layer and passivation layer wherein at least one chip contact pad contacts first electrically conductive layer; at least one cavity formed in first encapsulation structure, wherein at least one cavity exposes a portion of first passivation layer covering at least one chip contact pad; second encapsulation structure disposed over first encapsulation structure and covering at least one cavity, wherein a chamber region over at least one chip contact pad is defined by at least one cavity and second encapsulation structure; wherein second encapsulation structure includes an inlet and outlet connected to chamber region, wherein inlet and outlet control an inflow and outflow of heat dissipating material to and from chamber region.