Conducting Pad Protection in Chip Package Fabrication
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Solution Overview
Problem
Existing chip packaging methods face issues with damage to conducting pads during the dicing process due to scrap residue and the challenge of selecting an effective etching stop layer to increase yield.
Innovation Solution
A chip protection layer or additional etching stop layer is applied to cover conducting pads before dicing, using materials like composite oxide/nitride layers or additional insulating/silicon nitride layers to prevent damage and optimize etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conducting pads are exposed during dicing, then electrical connectivity is maintained, but conducting pads are damaged by scrap residue
Solution Approach 1:
A protective layer is formed over the conducting pads before the dicing process begins. This preliminary protective action prevents scrap residue from directly contacting and damaging the conducting pads during dicing, while allowing the dicing process to proceed normally.
Solution Approach 2:
The protective layer acts as an intermediary barrier between the conducting pads and the harmful dicing residue. This intermediate layer absorbs or deflects the harmful effects of scrap residue, preventing direct damage to the conducting pads while maintaining the dicing process efficiency.
2Manufacturing precision
If etching is performed on silicon substrate, then structural modification is achieved, but yield is reduced due to inadequate etching stop layer
Solution Approach 1:
An etching stop layer is deposited on the silicon substrate before the etching process. This preliminary layer serves as a controlled termination point for etching, preventing over-etching and ensuring precise etching depth control, thereby improving both etching precision and manufacturing yield.
Solution Approach 2:
The etching stop layer changes the etching parameters by providing a distinct material interface with different etching rates. This allows precise control of etching depth and termination, improving manufacturing precision and reducing defect rates that would otherwise reduce yield.
Data Source
AI summary
An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.