Multi-Die Chip Package Structure With Conductive Columns for Low Warpage
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Solution Overview
Problem
The challenge in semiconductor technologies is the low board level reliability of chip package structures due to varying coefficients of thermal expansion, leading to stress, warpage, and incomplete underfilling in large-scale multi-die packaging, which complicates the bonding process and reduces product yield.
Innovation Solution
A chip package structure and packaging method involving conductive columns directly grown on a substrate, eliminating the need for solder bonding and allowing separate coupling of chips through a connection chip, which simplifies the process, reduces stress, and enhances signal conduction and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-die packaging with large chip package structure is used to achieve high integration, then integration level is improved, but stress and warpage increase due to varying coefficients of thermal expansion
Solution Approach 1:
The patent segments the large chip package structure into multiple smaller independent bonding areas, each with its own connection chip. This segmentation reduces the overall stress and warpage by distributing the thermal expansion differences across multiple smaller interfaces rather than one large interface, thereby maintaining structural stability while achieving high integration.
Solution Approach 2:
The patent introduces connection chips as intermediary elements between the substrate and the chips to be packaged. These connection chips serve as mediators that reduce the direct bonding area between the substrate and multiple chips, thereby reducing stress and warpage while still enabling high-level integration through the network of connections.
2Adaptability or versatility
If large-area multi-die packaging structure is used to achieve high integration, then integration level is improved, but bonding process becomes more difficult and incomplete underfilling occurs
Solution Approach 1:
The patent divides the bonding process into multiple smaller bonding operations, each involving a single chip and connection chip pair. This segmentation makes the bonding process more manageable and controllable, reducing the likelihood of incomplete underfilling and bonding defects while achieving high integration through cumulative connections.
Solution Approach 2:
The patent uses connection chips that extend beyond the minimal necessary connection points, providing excess bonding area and underfill material pathways. This partial or excessive action ensures complete underfilling and reliable bonding by providing margin for manufacturing variations while maintaining high integration capability.
3Ease of manufacture
If conductive columns are directly grown on substrate to simplify process, then manufacturing complexity is reduced, but signal conduction and bonding stability must be maintained
Solution Approach 1:
The patent employs a self-service mechanism where conductive columns are directly grown on the substrate through electroplating, eliminating the need for separate solder bonding processes. This self-forming conductive structure simplifies manufacturing while maintaining reliable signal conduction and bonding stability through the direct metallurgical connection.
Solution Approach 2:
The patent changes the physical and chemical parameters of the substrate surface to enable direct growth of conductive columns. By controlling plating parameters such as current density, electrolyte composition, and growth time, the patent achieves reliable signal conduction and bonding stability through directly grown conductive structures rather than traditional solder joints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves board level reliability by reducing stress and warpage, enhancing signal conduction, and increasing product yield through simpler and more stable chip packaging, while allowing for higher integration and flexibility in multi-die packaging.
Implementation Method 1
the conductive columns are directly grown on the first surface of the substrate
Data Source
AI summary
A chip package structure includes: a substrate, a first connection chip, conductive columns, a first packaging layer, a first chip, and a second chip. The first connection chip is disposed on the substrate. The conductive columns is disposed on the substrate and located on a periphery of the first connection chip. The first packaging layer is disposed on the substrate and wrapping the first connection chip and the conductive columns, with the active surface of the first connection chip and top surfaces of the conductive columns exposed. The first chip is disposed on the first packaging layer, and coupled to both the conductive columns and the first connection chip. The second chip is disposed on the first packaging layer and that is away from the substrate, and coupled to both the conductive columns and the first connection chip.