Chip Package Structure with Conductive Post and Lead Frame
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Solution Overview
Problem
Traditional chip package assemblies face issues with high package resistance and reliability due to slender metal wires and pseudo soldering, which become inadequate as electronic devices become thinner, requiring a more efficient and reliable connection method.
Innovation Solution
A chip package structure that includes a lead frame with a conductive post and electrical connector, fully encapsulated by a plastic package, exposing the conductive post and connector on one surface and the lead on another, allowing for a thinner and more reliable electrical connection without pseudo soldering, achieved through a method involving a lead frame, conductive posts, and a plastic encapsulation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If slender metal wires are used to lead out electrodes on the chip surface, then the chip package can be assembled, but the package resistance becomes relatively large
Solution Approach 1:
The patent extracts the problematic slender metal wire bonding and replaces it with a direct lead frame connection structure. The lead frame's leads are directly connected to the chip electrodes through soldering or other bonding methods, eliminating the intermediate wire bonding step and reducing package resistance while simplifying the overall connection structure.
Solution Approach 2:
The patent transitions from a traditional wire bonding approach (three-dimensional space-consuming) to a planar lead frame structure where connections are made in the same plane as the chip. This dimensional reorganization reduces the path length and resistance while maintaining electrical connectivity.
2Reliability
If traditional lead bonding approaches are used, then the chip can be connected to external circuitry, but the reliability is adversely affected due to pseudo soldering between metal wires and chip pads
Solution Approach 1:
The patent removes the problematic wire bonding step that causes pseudo soldering issues. By using direct lead frame connections to chip electrodes, the intermediate wire bonding process is eliminated, thereby removing the source of reliability problems associated with pseudo soldering between metal wires and chip pads.
3Length of moving object
If traditional lead bonding approaches are used, then the chip can be connected to external circuitry, but the package thickness does not satisfy modern thin device requirements
Solution Approach 1:
The patent reorganizes the connection architecture from a vertical wire bonding approach to a planar integration approach using the lead frame. This allows the chip to be mounted directly on the lead frame carrier substrate with connections made in the same plane, dramatically reducing the overall package thickness while maintaining reliable electrical connections through direct bonding.
Data Source
AI summary
A chip package structure can include: a lead frame having a carrier substrate and a first lead around the carrier substrate; a first conductive post arranged on the first lead and electrically coupled with the first lead; a first chip having an active face and an inactive face opposite to the active face and attached to the carrier substrate, and electrode pads on the active face are provided with a first electrical connector; a first plastic package configured to fully encapsulate the first chip, and to partly encapsulate the lead frame, where the first plastic package includes a first surface and a second surface opposite to the first surface, where the first conductive post and the first electrical connector are exposed on the first surface, and where the first lead is exposed on the second surface, and a second lead being arranged on the first surface.