Chip Package Structure With Wafer-Defined Conductive Routing
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Solution Overview
Problem
The existing chip packaging process faces deviations in mounting and fixing chips onto carriers, leading to inaccuracies in laser drilling, which results in insufficient processing precision and reduced product yield due to the reliance on carrier-based references rather than chip-based benchmarks.
Innovation Solution
The method involves using chips on a wafer as processing benchmarks to produce conductive structures directly on the chips, eliminating the need for laser drilling and subsequent metal layer covering, thereby ensuring accurate placement and protection of PADs during the packaging process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If laser drilling is performed based on carrier position as reference, then the packaging process can be completed, but the processing precision deteriorates due to cumulative deviations from chip mounting, carrier positioning, and laser drilling
Solution Approach 1:
The patent applies preliminary action by forming conductive structures on the wafer before chip mounting. The conductive structures are created at predetermined positions corresponding to chip PADs, so that when chips are mounted, the conductive structures are already in place to receive balls and form electrical connections. This eliminates the need for post-mounting laser drilling and metal layer filling, thereby improving positioning accuracy and simplifying the overall process.
2Productivity
If multiple deviation sources (chip mounting, plastic packaging, laser drilling) are accumulated, then the packaging process can proceed, but the product yield deteriorates due to inability of metal layers to lead out PADs
Solution Approach 1:
The conductive structures are formed on the wafer before chip mounting, establishing accurate electrical connection paths in advance. This preliminary formation ensures that the conductive structures are precisely positioned relative to chip PADs, eliminating the need for subsequent laser drilling and metal layer filling that would introduce positioning deviations and affect connection reliability.
3Manufacturing precision
If traditional laser drilling and metal layer covering processes are used, then electrical connections can be established, but the processing precision deteriorates due to deviation from chip PAD positions
Solution Approach 1:
The conductive structures are formed on the wafer before chip mounting, establishing accurate electrical connection paths in advance. This preliminary formation ensures that the conductive structures are precisely positioned relative to chip PADs, eliminating the need for subsequent laser drilling and metal layer filling that would introduce positioning deviations and affect connection reliability.
Solution Approach 2:
The patent extracts and eliminates the laser drilling and metal layer filling steps from the traditional packaging process. By forming conductive structures on the wafer before chip mounting, the process removes the problematic post-mounting steps that cause positioning deviations, thereby improving both precision and efficiency.
Data Source
AI summary
The present disclosure relates to the technical field of semiconductors, and particularly discloses a preparation method of a chip package structure and a package structure. The preparation method of a chip package structure includes the following steps: providing a wafer and producing conductive structures on the wafer based on chip distribution; performing wafer dicing based on the chip distribution to obtain chip monomers; producing plastic package bodies including a plurality of chip monomers based on the chip monomers; and producing electric connection structures on the plastic package bodies. The preparation method of a chip package structure omits the processes of laser drilling and later metal layer covering, eliminates a deviation caused by laser drilling, and improves the processing precision of the package structure, thereby improving the yield of products, simplifying the whole chip packaging process, and effectively improving the packaging efficiency.