Chip Package with Coplanar Conductive Structures in Insulator
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Solution Overview
Problem
The challenge in chip packaging is the limited size of printed circuit boards, which hinders the miniaturization of electronic products due to the separate and independent disposition of sensing chips and integrated circuit chips, requiring a more efficient packaging method to reduce size and enhance connectivity.
Innovation Solution
A chip package design that integrates a sensing device with conductive structures and an integrated circuit device, covered by an insulating layer with holes, allowing for coplanar surfaces and reduced height, enabling wafer-level packaging and system-in-package formation to minimize board size and facilitate electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If sensing chips and integrated circuit chips are separately and independently disposed on a printed circuit board, then electrical connection between sensing functions and integrated circuits is achieved, but the size of the printed circuit board and electronic products increases
Solution Approach 1:
The patent merges the sensing device and integrated circuit device into a single chip package structure. The sensing device is disposed on a substrate with conductive structures, and the integrated circuit device is mounted on the same substrate, eliminating the need for separate PCB placement and wire connections. This consolidation directly reduces the overall size of electronic products while maintaining electrical connectivity.
Solution Approach 2:
The patent implements a nested structure where the integrated circuit device is mounted on top of the substrate that already contains the sensing device. The insulating layer with conductive structures is nested between these components, creating a compact stacked arrangement. This nesting approach minimizes the footprint and volume of the chip package compared to lateral separation on a PCB.
2Length of stationary object
If sensing chips and integrated circuit chips are separately disposed and connected through wires, then electrical connection is established, but the height and complexity of the packaging structure increases
Solution Approach 1:
The patent transitions from a lateral two-dimensional layout on a PCB to a vertical three-dimensional stacked architecture. The sensing device, insulating layer with conductive structures, and integrated circuit device are arranged in vertical layers, utilizing the height dimension efficiently. This dimensional change reduces the horizontal footprint and overall package complexity while maintaining electrical connections through vertical conductive pathways.
Solution Approach 2:
The patent introduces an insulating layer with integrated conductive structures as an intermediary between the sensing device and integrated circuit device. This intermediary layer provides both electrical connection pathways and mechanical support, eliminating the need for external wire connections and simplifying the overall packaging structure. The conductive structures within the insulating layer serve as built-in interconnects that reduce package height and complexity.
3Ease of manufacture
If separate chip packages are used for sensing functions and integrated circuits, then independent functionality is maintained, but fabrication cost and board size increase
Solution Approach 1:
The patent combines multiple functional components (sensing device, integrated circuit device, and interconnect structures) into a single integrated chip package. This merging eliminates the need for separate PCB real estate for each component and reduces the number of assembly steps, thereby lowering fabrication costs and reducing the overall board size required.
Solution Approach 2:
The substrate in the patent serves multiple functions simultaneously: it supports the sensing device, provides mechanical structure, contains conductive interconnect structures for electrical connections, and serves as the mounting platform for the integrated circuit device. This multi-functionality reduces the number of separate components needed, simplifying manufacturing and reducing material costs.
Data Source
AI summary
A chip package is provided. The chip package includes a sensing device. The chip package also includes a first conductive structure disposed on the sensing device and electrically connected to the sensing device. The chip package further includes a chip and a second conductive structure disposed on the sensing device. The chip includes an integrated circuit device. The second conductive structure is positioned on the chip and is electrically connected to the integrated circuit device and the first conductive structure. In addition, the chip package includes an insulating layer covering the sensing device and the chip. The insulating layer has a hole. The first conductive structure is positioned under the bottom of the hole. The top surface of the insulating layer is coplanar with the top surface of the second conductive structure. A method for forming the chip package is also provided.