Chip Package Coplanarity Control via Encapsulant Extension Features

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

In package-on-package solutions, the bottom chip package often suffers from poor coplanarity due to thermal processing, leading to yield loss and unreliable solder joints between stacked packages.

Innovation Solution

The implementation of extension features formed from an encapsulant extending from the cap to the perimeter of the substrate, ensuring that at least two bond pads remain exposed to improve coplanarity and rigidity, thereby enhancing the bonding quality between stacked chip packages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the substrate is fully encapsulated to protect the integrated circuit, then protection is improved, but coplanarity deteriorates due to warpage

Engineering Contradiction:

Improveprotection of integrated circuitVSAvoidcoplanarity of substrate

Core Design Contradiction:

ReliabilityVSShape

Solution Approach 1:

The encapsulation is segmented into two distinct regions: a first encapsulant region that fully encapsulates the integrated circuit for protection, and a second encapsulant region that extends to the substrate perimeter to provide coplanarity. This segmentation allows each region to fulfill its specific function independently, resolving the contradiction between protection and shape maintenance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the encapsulation are given different qualities and extensions. The first encapsulant region provides protective encapsulation around the IC, while the second encapsulant region extends to the substrate perimeter to counteract warpage. This local differentiation allows the encapsulation to simultaneously provide both protection and coplanarity control.

Inventive Principle:

Principle #3Local quality

2Shape

If extension features are added to improve coplanarity, then coplanarity is improved, but device complexity increases

Engineering Contradiction:

Improvecoplanarity of substrateVSAvoidencapsulation structure

Core Design Contradiction:

ShapeVSDevice complexity

Solution Approach 1:

The coplanarity extension features are merged with the encapsulation structure itself, forming an integrated solution rather than adding separate components. The second encapsulant region serves dual purposes: maintaining coplanarity and providing structural support, thereby improving shape without proportionally increasing device complexity.

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If bond pads are covered by encapsulant for protection, then protection is improved, but electrical connectivity deteriorates

Engineering Contradiction:

Improveprotection of bond padsVSAvoidexposure of bond pads for soldering

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The encapsulation structure applies local quality differentiation by providing full encapsulation in the first region for IC protection while maintaining bond pad exposure in the second region for electrical connectivity. This localized approach ensures each area receives the treatment appropriate for its functional requirements.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS8836143B2Chip package with coplanarity controlling feature

Publication Date: 2014.09.16 STMICROELECTRONICS INT NV

AI summary

A chip package includes a substrate, an integrated circuit proximate a top surface of the substrate, and a cap comprising encapsulant that encapsulates the integrated circuit on at least a portion of the top surface of the substrate. The chip package further includes at least one extension feature positioned on at least a portion of the top surface of the substrate. The at least one extension feature also comprises the encapsulant and extends from the cap to a perimeter of the substrate.