Chip Package Structure Without Core Dielectric Layer
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Solution Overview
Problem
Conventional chip package manufacturing processes are hindered by the thickness of the core dielectric layer, which limits the reduction of chip package thickness and increases production costs.
Innovation Solution
A manufacturing process that eliminates the core dielectric layer by using a patterned conductive layer with first and second patterned solder resist layers, where chips are bonded to the first patterned solder resist layer and electrically connected to the conductive layer through bonding wires, and encapsulated with a molding compound, allowing for thinner chip packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a core dielectric layer is used in conventional circuit board manufacturing, then structural stability and electrical insulation are improved, but the overall thickness of the chip package increases
Solution Approach 1:
The patent removes the core dielectric layer from the traditional circuit board structure, extracting only the essential functional elements (conductive layers and solder resist layers) while eliminating the thick insulating core that contributes to overall package thickness
Solution Approach 2:
The patent transitions from a multi-layer stacked structure with significant thickness to a thin-film planar structure where conductive and solder resist layers are deposited in alternating patterns on a substrate, achieving the same electrical functionality in a much thinner profile
2Reliability
If a core dielectric layer is used in conventional circuit board manufacturing, then electrical insulation is improved, but production costs increase
Solution Approach 1:
The patent eliminates the core dielectric layer and its associated manufacturing processes (laminating, curing, drilling, plating through-holes), significantly reducing production complexity and cost while maintaining electrical insulation through the solder resist layer pattern design
Solution Approach 2:
The patent changes the structural parameters from thick layered construction to thin-film deposition, reducing material consumption and manufacturing steps while achieving equivalent or superior electrical insulation performance through optimized layer patterning
3Strength
If a core dielectric layer is used in conventional circuit board manufacturing, then structural support is improved, but manufacturing complexity increases
Solution Approach 1:
The patent removes the core dielectric layer and its complex manufacturing workflow (laminating, drilling, plating, multiple patterning steps), replacing it with a simplified sequential process of depositing conductive layers and solder resist layers that requires fewer manufacturing steps and less equipment
Solution Approach 2:
The patent segments the manufacturing process into distinct sequential steps (deposit conductive layer, pattern solder resist, etch conductive layer, repeat) that can be performed independently and systematically, reducing overall process complexity compared to traditional simultaneous multi-layer construction
Data Source
AI summary
A manufacturing process for a chip package structure is provided. First, a patterned conductive layer having a plurality of first openings and a first patterned solder resist layer on the patterned conductive layer are provided. A second patterned solder resist layer is formed on the patterned conductive layer such that the first patterned solder resist layer and the second patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. Chips are bonded onto the first patterned solder resist layer such that the first patterned solder resist layer is between the chips and the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings. At least one molding compound is formed and the molding compound, the first patterned solder resist layer and the second patterned solder resist layer are separated.