Chip Package PDN Layout for Balanced Current Distribution
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Solution Overview
Problem
Conventional chip packaging designs face issues with non-uniform current distribution, leading to high current crowding and electromigration reliability problems, which are often discovered late in the design cycle, causing additional iterations and delays.
Innovation Solution
A chip package with a power delivery network (PDN) featuring non-uniform electrical conductance, where current paths are designed with varying electrical conductance to balance current flow across the package, using current control connections to mitigate high current regions and promote balanced distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voids are created in the ground plane to balance current variation, then current distribution is improved, but DC loop resistance and DC internal resistance increase
Solution Approach 1:
The patent applies local quality by creating non-uniform electrical conductance in specific regions of the PDN. Current control connections with varying conductance values are strategically placed in different areas of the package substrate to locally adjust current distribution. This allows current crowding to be mitigated in high-current regions without creating ground plane voids that would increase overall resistance.
Solution Approach 2:
The patent changes the electrical conductance parameter of current control connections to achieve balanced current distribution. By varying the conductance values of different current control connections, the system optimizes current flow paths without compromising the integrity of the ground plane, thereby avoiding increased DC loop resistance while still addressing current distribution issues.
2Reliability
If voids are created in the ground plane to balance current variation, then current distribution is improved, but design iteration increases
Solution Approach 1:
The patent implements preliminary action by incorporating current control connections with non-uniform electrical conductance into the PDN design from the beginning. This proactive approach allows current distribution issues to be addressed during the initial design phase rather than being discovered later during final design review, thereby reducing the need for iterative redesigns and associated delays.
3Power
If PDN is centered near the middle of the IC die, then power delivery is optimized, but current crowding occurs near capacitors
Solution Approach 1:
The patent applies local quality by placing current control connections with specifically tuned conductance values near the centrally located capacitors. These local adjustments to electrical conductance in high-current regions prevent current crowding and electromigration issues while preserving the overall centralized PDN architecture that provides optimized power delivery to the IC die.
Data Source
AI summary
A chip package and method for fabricating the same are provided that includes a power delivery network (PDN) with non-uniform electrical conductance. The electrical conductance through each current path of the PDN may be selected to balance the distribution of current flow across the current paths through the chip package, thus compensating for areas of high and low current draw found in conventional designs.