Chip Package Tracking via Dam Layer Mark Portions

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The miniaturization of integrated circuit wafers makes it difficult to track them during the production process, leading to increased manufacturing costs and time due to the need for additional processes to create identifying numbers.

Innovation Solution

A chip package design that incorporates a sensing element, a dam layer with patterned mark portions, and a light transmissive cover, allowing for tracking without additional manufacturing steps by forming the mark portions in the same patterning step as the dam layer, thereby reducing costs and production time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If additional manufacturing process is used to create numbers on wafers for tracking, then tracking capability is improved, but manufacturing cost and production time increase

Engineering Contradiction:
Improvetracking informationVSAvoidmanufacturing cost
Core Design Contradiction:
Loss of informationVSEase of manufacture

Solution Approach 1:

The patent combines the wafer tracking mark formation with the existing sensor electrode patterning process. The resist material used for patterning the sensor electrodes simultaneously forms the tracking marks when applied to the back surface of the wafer, eliminating the need for separate marking operations and reducing manufacturing costs.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The resist material and patterning process serve multiple functions: they define the sensor electrode patterns on the front surface and simultaneously create the tracking identification marks on the back surface. This multi-functional approach eliminates dedicated marking processes and reduces overall manufacturing complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Loss of information

If additional manufacturing process is used to create numbers on wafers for tracking, then tracking capability is improved, but production time increases

Engineering Contradiction:
Improvetracking informationVSAvoidproduction time
Core Design Contradiction:
Loss of informationVSProductivity

Solution Approach 1:

The patent merges the tracking mark formation with the sensor electrode patterning steps. By applying a single resist layer to the back surface that patterns both the electrode connections and the tracking marks simultaneously, the process eliminates sequential operations and reduces total production time.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The tracking marks are formed during the initial patterning stages before wafer fabrication is complete. By creating the identification marks early in the manufacturing process rather than adding them later, the patent eliminates post-processing steps and accelerates production.

Inventive Principle:
Principle #10Preliminary action

3Volume of moving object

If wafer size is reduced for miniaturization, then device integration is improved, but tracking difficulty increases

Engineering Contradiction:
Improvewafer sizeVSAvoidtracking difficulty
Core Design Contradiction:
Volume of moving objectVSDifficulty of detecting and measuring

Solution Approach 1:

The patent places the tracking marks on the back surface of the wafer, utilizing the third dimension (depth/thickness) to resolve the tracking difficulty. This spatial separation allows tracking marks to be positioned away from the miniaturized front surface features, making them detectable despite the reduced wafer dimensions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent applies different functional qualities to different surfaces of the wafer: the front surface contains the miniaturized sensor elements while the back surface contains the tracking marks. This local differentiation allows each surface to optimize its specific function without compromising the other, enabling tracking on small wafers.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20230230933A1Chip package and manufacturing method thereof
Publication Date: 2023.07.20 XINTEC INC
  • US20230230933A1 patent drawing
  • US20230230933A1 patent drawing
  • US20230230933A1 patent drawing

AI summary

A chip package includes a sensing element, a dam layer, and a light transmissive cover. A surface of the sensing element has a sensing area and a conductive pad. The conductive pad is adjacent to an edge of the surface of the sensing element. The dam layer is located on the surface of the sensing element and surrounds the sensing area. The dam layer has a main portion and plural mark portions. The mark portions are respectively located in plural corners of the main portion, located in a sidewall of the main portion, respectively located on plural corners of the sensing element, respectively located on plural inner edges of the main portion, or respectively located on plural outer edges of the main portion. The light transmissive cover is located on the dam layer.