Chip Package Redistribution Structure for Planar Dense Wiring

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Solution Overview

Problem

Current semiconductor packaging technologies face challenges in achieving high yield and efficient signal transmission and power connection due to planarity and wiring density issues in redistribution structures, leading to suboptimal bonding processes and increased costs.

Innovation Solution

The formation of redistribution structures over carrier substrates using layer-by-layer deposition improves planarity and wiring density, with conductive bumps and molding layers enhancing bonding efficiency and reducing warpage, while interposer substrates with conductive via structures and insulating layers facilitate better electrical connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional packaging technologies are used, then manufacturing simplicity is maintained, but planarity and wiring density of redistribution structures deteriorate

Engineering Contradiction:

Improveplanarity and wiring density of redistribution structuresVSAvoidcomplexity of layer-by-layer deposition process

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The redistribution structure is divided into multiple layers (first redistribution layer, second redistribution layer, etc.) that are formed separately and then integrated. Each layer can be optimized independently for planarity and wiring density, resolving the contradiction between manufacturing precision and device complexity by breaking down the complex structure into manageable segments.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The carrier substrate is prepared in advance with predefined patterns and structures before the actual device assembly. This preliminary preparation ensures that when layers are deposited and bonded, the planarity and wiring density requirements are already satisfied, reducing the complexity of subsequent manufacturing steps.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If bonding process is optimized for high yield, then production efficiency improves, but warpage and planarity issues worsen

Engineering Contradiction:

Improveyield of bonding processVSAvoidwarpage and planarity of structures

Core Design Contradiction:

ProductivityVSStability of the object's composition

Solution Approach 1:

The patent introduces counterbalancing structures such as support layers and strategically placed conductive bumps that compensate for warpage tendencies. These counterweight elements balance the internal stresses that cause warpage during bonding, allowing high-yield bonding processes without compromising planarity and structural stability.

Inventive Principle:

Principle #8Anti-weight (Counterweight)

Solution Approach 2:

The patent modifies material parameters such as selecting specific materials with matched thermal expansion coefficients, adjusting deposition parameters to control layer stress, and optimizing bonding temperature and pressure parameters. These parameter changes enable high-yield bonding while maintaining warpage control and planarity.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If wiring density is increased for better signal transmission, then electrical performance improves, but manufacturing difficulty increases

Engineering Contradiction:

Improvesignal transmission and power connection efficiencyVSAvoiddifficulty of forming dense wiring structures

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent transitions from planar two-dimensional wiring to three-dimensional multi-layer wiring structures. By adding the vertical dimension with multiple stacked redistribution layers, the patent achieves higher effective wiring density and better electrical performance while maintaining manufacturability through standard multi-layer deposition and bonding techniques.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces intermediate layers such as dielectric layers, adhesive layers, and support layers between the conductive wiring layers. These intermediary layers facilitate the manufacturing of dense wiring structures by providing mechanical support, electrical isolation, and stress management, making it easier to achieve high wiring density without excessive manufacturing difficulty.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11756892B2Method for forming chip package structure

Publication Date: 2023.09.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method for forming a chip package structure is provided. The method includes forming a first redistribution structure over a first carrier substrate. The method includes bonding a chip structure to the first surface through a first conductive bump. The method includes forming a first molding layer over the first redistribution structure. The method includes removing the first carrier substrate. The method includes forming a second conductive bump over the second surface. The method includes forming a second redistribution structure over a second carrier substrate. The method includes bonding the first redistribution structure to the third surface. The method includes forming a second molding layer over the second redistribution structure. The method includes removing the second carrier substrate. The method includes removing a portion of the second redistribution structure from the fourth surface. The method includes forming a third conductive bump over the fourth surface.