Chip Package Singulation Through Etched Low-k Dielectric Openings
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Solution Overview
Problem
The brittle nature of low-k dielectric material in chip packages makes them prone to defects such as debris, cracks, and rough sidewalls during the singulation process, leading to reduced yield and reliability.
Innovation Solution
A method involving the formation of a masking layer with specific openings, followed by an etching process to create openings in the dielectric layer, and finally a sawing process through these openings to separate chip regions, thereby minimizing mechanical and thermal stress on the dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a laser process or dicing saw process is used for singulation, then chip packages can be formed and separated, but the brittle dielectric material layer is prone to defects such as debris, cracks, and rough sidewalls
Solution Approach 1:
The method performs preliminary actions by forming a masking layer with openings and etching the dielectric layer before the final sawing process. This pre-preparation creates controlled pathways that guide the subsequent sawing, preventing uncontrolled stress concentration and defect formation in the brittle dielectric material during separation.
Solution Approach 2:
The masking layer serves as an intermediary element between the sawing tool and the dielectric material. It provides a structured interface that controls the interaction during singulation, allowing the saw to cut through predetermined paths while the etched openings in the dielectric layer reduce mechanical stress concentration, thereby preventing cracks and debris formation.
2Volume of moving object
If the dielectric material layer is made thinner to reduce package size, then integration density increases, but the layer becomes more susceptible to mechanical stress and thermal stress during processing
Solution Approach 1:
The method applies local quality by creating openings in the dielectric layer at specific locations (in the scribe-line region) rather than uniformly throughout. This localized modification reduces stress concentration at critical points during thinning and sawing processes, allowing thinner dielectric layers to maintain sufficient mechanical strength despite reduced overall thickness for miniaturization.
3Device complexity
If conventional singulation methods are used without pre-etching, then the process is simpler and faster, but defects such as cracks and rough sidewalls occur frequently
Solution Approach 1:
The method performs preliminary etching of the dielectric layer through openings in the masking layer before the final sawing operation. This pre-etching creates smooth-walled openings that serve as stress-relief pathways, preventing crack formation and ensuring clean cuts during subsequent sawing, thereby improving manufacturing precision without significantly increasing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the occurrence of defects in the dielectric layer, enhances the reliability of chip packages, and improves the precision and control of the sawing process.
Implementation Method 1
forming a masking layer over the substrate to cover the dielectric layer
Implementation Method 2
performing an etching process on the dielectric layer to form a second opening in the dielectric layer directly below the first opening
Implementation Method 3
performing a sawing process on the substrate through the second opening
Data Source
AI summary
Chip packages and methods for forming the same are provided. The method includes providing a substrate having upper and lower surfaces, and having a chip region and a scribe-line region surrounding the chip region. The substrate has a dielectric layer on its upper surface. A masking layer is formed over the substrate to cover the dielectric layer. The masking layer has a first opening exposing the dielectric layer and extending in the extending direction of the scribe-line region to surround the chip region. An etching process is performed on the dielectric layer directly below the first opening, to form a second opening that is in the dielectric layer directly below the first opening. The masking layer is removed to expose the dielectric layer having the second opening. A dicing process is performed on the substrate through the second opening.